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ac/llvm: Remove now-superfluous intrinsics and ABI callbacks.

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Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13155>
This commit is contained in:
Timur Kristóf 2022-03-23 19:25:38 +01:00 • committed by Marge Bot
parent f553076eaf
commit 27c4d8d5fa
3 changed files with 0 additions and 82 deletions
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45
src/amd/llvm/ac_nir_to_llvm.c
View file

@ -4074,36 +4074,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
case nir_intrinsic_load_patch_vertices_in:
result = ctx->abi->load_patch_vertices_in(ctx->abi);
break;
case nir_intrinsic_load_tess_rel_patch_id_amd:
if (ctx->stage == MESA_SHADER_TESS_CTRL)
result = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->tcs_rel_ids), 0, 8);
else if (ctx->stage == MESA_SHADER_TESS_EVAL)
result = ctx->tes_rel_patch_id_replaced ? ctx->tes_rel_patch_id_replaced
: ac_get_arg(&ctx->ac, ctx->args->tes_rel_patch_id);
else
unreachable("tess_rel_patch_id_amd is only supported by tessellation shaders");
break;
case nir_intrinsic_load_ring_tess_factors_amd:
result = ctx->abi->load_ring_tess_factors(ctx->abi);
break;
case nir_intrinsic_load_ring_tess_factors_offset_amd:
result = ac_get_arg(&ctx->ac, ctx->args->tcs_factor_offset);
break;
case nir_intrinsic_load_ring_tess_offchip_amd:
result = ctx->abi->load_ring_tess_offchip(ctx->abi);
break;
case nir_intrinsic_load_ring_tess_offchip_offset_amd:
result = ac_get_arg(&ctx->ac, ctx->args->tess_offchip_offset);
break;
case nir_intrinsic_load_ring_esgs_amd:
result = ctx->abi->load_ring_esgs(ctx->abi);
break;
case nir_intrinsic_load_ring_es2gs_offset_amd:
result = ac_get_arg(&ctx->ac, ctx->args->es2gs_offset);
break;
case nir_intrinsic_load_gs_vertex_offset_amd:
result = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[nir_intrinsic_base(instr)]);
break;
case nir_intrinsic_vote_all: {
result = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
break;
@ -4300,15 +4270,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
cache_policy);
break;
}
case nir_intrinsic_load_packed_passthrough_primitive_amd:
result = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]);
break;
case nir_intrinsic_load_initial_edgeflags_amd:
if (ctx->stage == MESA_SHADER_VERTEX && !ctx->info->vs.blit_sgprs_amd)
result = ac_pack_edgeflags_for_export(&ctx->ac, ctx->args);
else
result = ctx->ac.i32_0;
break;
case nir_intrinsic_has_input_vertex_amd: {
LLVMValueRef num =
ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 0, 8);
@ -4321,12 +4282,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
result = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), num, "");
break;
}
case nir_intrinsic_load_workgroup_num_input_vertices_amd:
result = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info), 12, 9);
break;
case nir_intrinsic_load_workgroup_num_input_primitives_amd:
result = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info), 22, 9);
break;
case nir_intrinsic_alloc_vertices_and_primitives_amd:
/* The caller should only call this conditionally for wave 0, so assume that the current
* wave is always wave 0.

6
src/amd/llvm/ac_shader_abi.h
View file

@ -78,12 +78,6 @@ struct ac_shader_abi {
LLVMValueRef (*load_patch_vertices_in)(struct ac_shader_abi *abi);
LLVMValueRef (*load_ring_tess_offchip)(struct ac_shader_abi *abi);
LLVMValueRef (*load_ring_tess_factors)(struct ac_shader_abi *abi);
LLVMValueRef (*load_ring_esgs)(struct ac_shader_abi *abi);
LLVMValueRef (*load_tess_level)(struct ac_shader_abi *abi, unsigned varying_id,
bool load_default_state);

31
src/amd/vulkan/radv_nir_to_llvm.c
View file

@ -303,34 +303,6 @@ visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
ctx->gs_wave_id);
}
static LLVMValueRef
load_ring_tess_factors(struct ac_shader_abi *abi)
{
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
assert(ctx->stage == MESA_SHADER_TESS_CTRL);
return ctx->hs_ring_tess_factor;
}
static LLVMValueRef
load_ring_tess_offchip(struct ac_shader_abi *abi)
{
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
assert(ctx->stage == MESA_SHADER_TESS_CTRL || ctx->stage == MESA_SHADER_TESS_EVAL);
return ctx->hs_ring_tess_offchip;
}
static LLVMValueRef
load_ring_esgs(struct ac_shader_abi *abi)
{
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
assert(ctx->stage == MESA_SHADER_VERTEX || ctx->stage == MESA_SHADER_TESS_EVAL ||
ctx->stage == MESA_SHADER_GEOMETRY);
return ctx->esgs_ring;
}
static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi *abi, bool non_indexed_is_zero)
{
@ -2072,9 +2044,6 @@ ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
ctx.abi.load_ubo = radv_load_ubo;
ctx.abi.load_ssbo = radv_load_ssbo;
ctx.abi.load_sampler_desc = radv_get_sampler_desc;
ctx.abi.load_ring_tess_factors = load_ring_tess_factors;
ctx.abi.load_ring_tess_offchip = load_ring_tess_offchip;
ctx.abi.load_ring_esgs = load_ring_esgs;
ctx.abi.clamp_shadow_reference = false;
ctx.abi.robust_buffer_access = options->robust_buffer_access;
ctx.abi.load_grid_size_from_user_sgpr = args->load_grid_size_from_user_sgpr;