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tu: Stop setting binning fields on a7xx

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These fields don't actually enable binning, but rather disables the FS.
This seems to happen automatically on a7xx when binning, because the
blob doesn't set them specially during the binning pass.

Move them to rasterization, because RB_RENDER_CNTL will start depending
on rasterization state in the next commit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33152>
This commit is contained in:
Connor Abbott 2025-01-21 17:49:37 -05:00 • committed by Marge Bot
parent ffe8220bbd
commit 2798521bda
3 changed files with 11 additions and 5 deletions
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5
src/freedreno/vulkan/tu_clear_blit.cc
View file

@ -955,6 +955,11 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type,
tu_cs_emit_regs(cs, A6XX_VPC_UNKNOWN_9107());
} else {
tu_cs_emit_regs(cs, A7XX_PC_RASTER_CNTL_V2());
tu_cs_emit_regs(cs, RB_RENDER_CNTL(CHIP,
.raster_mode = TYPE_TILED,
.raster_direction = LR_TB));
tu_cs_emit_regs(cs, A7XX_GRAS_SU_RENDER_CNTL());
}
tu_cs_emit_regs(cs,

4
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -697,10 +697,6 @@ tu6_emit_render_cntl<A7XX>(struct tu_cmd_buffer *cmd,
struct tu_cs *cs,
bool binning)
{
tu_cs_emit_regs(
cs, RB_RENDER_CNTL(A7XX, .binning = binning, .raster_mode = TYPE_TILED,
.raster_direction = LR_TB));
tu_cs_emit_regs(cs, A7XX_GRAS_SU_RENDER_CNTL(.binning = binning));
}
static void

7
src/freedreno/vulkan/tu_pipeline.cc
View file

@ -3106,7 +3106,7 @@ tu6_rast_size(struct tu_device *dev,
if (CHIP == A6XX) {
return 15 + (dev->physical_device->info->a6xx.has_legacy_pipeline_shading_rate ? 8 : 0);
} else {
return 17;
return 21;
}
}
@ -3167,6 +3167,11 @@ tu6_emit_rast(struct tu_cs *cs,
tu_cs_emit_regs(cs, A7XX_PC_RASTER_CNTL_V2(
.stream = rs->rasterization_stream,
.discard = rs->rasterizer_discard_enable));
tu_cs_emit_regs(cs, RB_RENDER_CNTL(CHIP,
.raster_mode = TYPE_TILED,
.raster_direction = LR_TB));
tu_cs_emit_regs(cs, A7XX_GRAS_SU_RENDER_CNTL());
}
/* move to hw ctx init? */