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r600: fix abs for op3 sources
If a src was referencing the same temp as the dst, the per-component copy code didn't work. e.g. cndge r0.xy, r0.xx, |r2|, r3 got expanded into mov r12.x, |r2| cndge r0.x, r0.x, r12, r3 mov r12.y, |r2| cndge r0.y, r0.x, r12, r3 hence for the second cndge r0.x was mistakenly the previous cndge result. Fix this by doing all the movs first, so there's no bogus alu.last in between. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=102905 Tested-by: <iive@yahoo.com> Reviewed-by: Dave Airlie <airlied@gmail.com>
This commit is contained in:
Roland Scheidegger
parent
27a5e5366e
commit
274f8bf05e
1 changed files with 56 additions and 54 deletions
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@ -7076,33 +7076,42 @@ static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instru
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}
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static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
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unsigned temp, int chan,
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unsigned writemask,
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struct r600_bytecode_alu_src *bc_src,
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const struct r600_shader_src *shader_src)
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{
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struct r600_bytecode_alu alu;
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int r;
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int i, r;
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int lasti = tgsi_last_instruction(writemask);
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int temp_reg = 0;
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r600_bytecode_src(bc_src, shader_src, chan);
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r600_bytecode_src(&bc_src[0], shader_src, 0);
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r600_bytecode_src(&bc_src[1], shader_src, 1);
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r600_bytecode_src(&bc_src[2], shader_src, 2);
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r600_bytecode_src(&bc_src[3], shader_src, 3);
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/* op3 operands don't support abs modifier */
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if (bc_src->abs) {
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assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP1_MOV;
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alu.dst.sel = temp;
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alu.dst.chan = chan;
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alu.dst.write = 1;
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temp_reg = r600_get_temp(ctx);
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alu.src[0] = *bc_src;
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alu.last = true; // sufficient?
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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memset(bc_src, 0, sizeof(*bc_src));
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bc_src->sel = temp;
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bc_src->chan = chan;
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for (i = 0; i < lasti + 1; i++) {
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if (!(writemask & (1 << i)))
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continue;
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP1_MOV;
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alu.dst.sel = temp_reg;
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alu.dst.chan = i;
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alu.dst.write = 1;
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alu.src[0] = bc_src[i];
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if (i == lasti) {
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alu.last = 1;
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}
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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memset(&bc_src[i], 0, sizeof(*bc_src));
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bc_src[i].sel = temp_reg;
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bc_src[i].chan = i;
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}
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}
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return 0;
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}
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@ -7111,9 +7120,9 @@ static int tgsi_op3_dst(struct r600_shader_ctx *ctx, int dst)
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{
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
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struct r600_bytecode_alu alu;
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struct r600_bytecode_alu_src srcs[4][4];
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int i, j, r;
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int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
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int temp_regs[4];
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unsigned op = ctx->inst_info->op;
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if (op == ALU_OP3_MULADD_IEEE &&
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@ -7121,10 +7130,12 @@ static int tgsi_op3_dst(struct r600_shader_ctx *ctx, int dst)
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op = ALU_OP3_MULADD;
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for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
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temp_regs[j] = 0;
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if (ctx->src[j].abs)
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temp_regs[j] = r600_get_temp(ctx);
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r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
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srcs[j], &ctx->src[j]);
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if (r)
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return r;
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}
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for (i = 0; i < lasti + 1; i++) {
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if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
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continue;
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@ -7132,9 +7143,7 @@ static int tgsi_op3_dst(struct r600_shader_ctx *ctx, int dst)
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = op;
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for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
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r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
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if (r)
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return r;
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alu.src[j] = srcs[j][i];
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}
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if (dst == -1) {
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@ -9386,7 +9395,8 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
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struct r600_bytecode_alu alu;
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unsigned lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
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unsigned i, temp_regs[2];
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struct r600_bytecode_alu_src srcs[2][4];
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unsigned i;
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int r;
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/* optimize if it's just an equal balance */
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@ -9456,14 +9466,13 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
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}
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/* src0 * src1 + (1 - src0) * src2 */
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if (ctx->src[0].abs)
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temp_regs[0] = r600_get_temp(ctx);
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else
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temp_regs[0] = 0;
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if (ctx->src[1].abs)
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temp_regs[1] = r600_get_temp(ctx);
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else
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temp_regs[1] = 0;
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for (i = 0; i < 2; i++) {
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r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
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srcs[i], &ctx->src[i]);
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if (r)
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return r;
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}
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for (i = 0; i < lasti + 1; i++) {
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if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
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@ -9472,12 +9481,8 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP3_MULADD;
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alu.is_op3 = 1;
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r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
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if (r)
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return r;
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r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
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if (r)
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return r;
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alu.src[0] = srcs[0][i];
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alu.src[1] = srcs[1][i];
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alu.src[2].sel = ctx->temp_reg;
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alu.src[2].chan = i;
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@ -9499,7 +9504,8 @@ static int tgsi_cmp(struct r600_shader_ctx *ctx)
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struct r600_bytecode_alu alu;
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int i, r, j;
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int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
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int temp_regs[3];
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struct r600_bytecode_alu_src srcs[3][4];
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unsigned op;
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if (ctx->src[0].abs && ctx->src[0].neg) {
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@ -9511,9 +9517,10 @@ static int tgsi_cmp(struct r600_shader_ctx *ctx)
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}
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for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
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temp_regs[j] = 0;
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if (ctx->src[j].abs)
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temp_regs[j] = r600_get_temp(ctx);
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r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
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srcs[j], &ctx->src[j]);
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if (r)
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return r;
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}
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for (i = 0; i < lasti + 1; i++) {
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@ -9522,15 +9529,10 @@ static int tgsi_cmp(struct r600_shader_ctx *ctx)
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = op;
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r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
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if (r)
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return r;
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r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
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if (r)
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return r;
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r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
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if (r)
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return r;
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alu.src[0] = srcs[0][i];
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alu.src[1] = srcs[2][i];
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alu.src[2] = srcs[1][i];
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tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
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alu.dst.chan = i;
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alu.dst.write = 1;
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