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freedreno/regs: a7xx has a new source type CP_REG_TEST

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Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
This commit is contained in:
Danylo Piliaiev 2023-07-05 16:04:49 +02:00 • committed by Marge Bot
parent 853d64ae55
commit 27312eb386
2 changed files with 20 additions and 12 deletions
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22
src/freedreno/.gitlab-ci/reference/fd-clouds.log
View file

@ -1473,7 +1473,7 @@ cmdstream[0]: 1023 dwords
gpuaddr:0000000001d90010
0000000001d918e0: 0000: 70c28003 00000883 01d90010 00000000
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d918f0: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
@ -1557,7 +1557,7 @@ cmdstream[0]: 1023 dwords
opcode: CP_SET_MODE (63) (2 dwords)
0000000001d919d0: 0000: 70e30001 00000000
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d919d8: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
@ -1707,7 +1707,7 @@ cmdstream[0]: 1023 dwords
:0,1,17,6
0000000001d91aa4: 0000: 48088901 00000011
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0xc38 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
{ SOURCE = SOURCE_REG | REG = 0xc38 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91aac: 0000: 70b90001 02000c38
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
@ -6749,7 +6749,7 @@ cmdstream[0]: 1023 dwords
:0,1,18,3
0000000001d91ad4: 0000: 48088901 00000012
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91adc: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
@ -6874,7 +6874,7 @@ cmdstream[0]: 1023 dwords
opcode: CP_SET_MODE (63) (2 dwords)
0000000001d91b9c: 0000: 70e30001 00000000
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91ba4: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
@ -6948,7 +6948,7 @@ cmdstream[0]: 1023 dwords
:0,1,27,24
0000000001d91c70: 0000: 48088901 0000001b
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0xc39 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
{ SOURCE = SOURCE_REG | REG = 0xc39 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91c78: 0000: 70b90001 02000c39
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
@ -6965,7 +6965,7 @@ cmdstream[0]: 1023 dwords
:0,1,28,24
0000000001d91ca0: 0000: 48088901 0000001c
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91ca8: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
@ -7043,7 +7043,7 @@ cmdstream[0]: 1023 dwords
opcode: CP_SET_MODE (63) (2 dwords)
0000000001d91d68: 0000: 70e30001 00000000
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91d70: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
@ -7117,7 +7117,7 @@ cmdstream[0]: 1023 dwords
:0,1,37,34
0000000001d91e3c: 0000: 48088901 00000025
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0xc3a | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
{ SOURCE = SOURCE_REG | REG = 0xc3a | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91e44: 0000: 70b90001 02000c3a
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
@ -7134,7 +7134,7 @@ cmdstream[0]: 1023 dwords
:0,1,38,34
0000000001d91e6c: 0000: 48088901 00000026
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91e74: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
@ -7212,7 +7212,7 @@ cmdstream[0]: 1023 dwords
opcode: CP_SET_MODE (63) (2 dwords)
0000000001d91f34: 0000: 70e30001 00000000
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91f3c: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }

10
src/freedreno/registers/adreno/adreno_pm4.xml
View file

@ -1783,9 +1783,17 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
offset 0x0c10 is 1
</doc>
<enum name="source_type">
<value value="0" name="SOURCE_REG"/>
<!-- Don't confuse with scratch registers, this is a separate memory
written into by CP_MEM_TO_SCRATCH_MEM. -->
<value value="1" name="SOURCE_SCRATCH_MEM" varset="chip" variants="A7XX-"/>
</enum>
<reg32 offset="0" name="0">
<!-- the register to test -->
<bitfield name="REG" low="0" high="17"/>
<bitfield name="REG" low="0" high="17" varset="source_type" variants="SOURCE_REG"/>
<bitfield name="SCRATCH_MEM_OFFSET" low="0" high="17" varset="source_type" variants="SOURCE_SCRATCH_MEM"/>
<bitfield name="SOURCE" pos="18" type="source_type" addvariant="yes"/>
<!-- the bit to test -->
<bitfield name="BIT" low="20" high="24" type="uint"/>
<!-- skip implied CP_WAIT_FOR_ME -->