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brw: Use brw prefix to LSC helpers tied to brw

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Mapping from BRW ops to LSC ops.  And the len() helpers
that use the REG_SIZE as unit -- which is a BRW convention.

Acked-by: Iván Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41006>
This commit is contained in:
Caio Oliveira 2026-03-18 15:09:21 -07:00 • committed by Marge Bot
parent e56354661b
commit 26ef12f7c1
5 changed files with 19 additions and 20 deletions
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10
src/intel/compiler/brw/brw_eu.h
View file

@ -982,7 +982,7 @@ lsc_op_num_data_values(unsigned _op)
}
static inline unsigned
lsc_op_to_legacy_atomic(unsigned _op)
brw_lsc_op_to_legacy_atomic(unsigned _op)
{
enum lsc_opcode op = (enum lsc_opcode) _op;
@ -1191,16 +1191,16 @@ lsc_msg_desc_cache_ctrl(UNUSED const struct intel_device_info *devinfo,
}
static inline unsigned
lsc_msg_dest_len(const struct intel_device_info *devinfo,
enum lsc_data_size data_sz, unsigned n)
brw_lsc_msg_dest_len(const struct intel_device_info *devinfo,
enum lsc_data_size data_sz, unsigned n)
{
return DIV_ROUND_UP(lsc_data_size_bytes(data_sz) * n,
reg_unit(devinfo) * REG_SIZE) * reg_unit(devinfo);
}
static inline unsigned
lsc_msg_addr_len(const struct intel_device_info *devinfo,
enum lsc_addr_size addr_sz, unsigned n)
brw_lsc_msg_addr_len(const struct intel_device_info *devinfo,
enum lsc_addr_size addr_sz, unsigned n)
{
return DIV_ROUND_UP(lsc_addr_size_bytes(addr_sz) * n,
reg_unit(devinfo) * REG_SIZE) * reg_unit(devinfo);

4
src/intel/compiler/brw/brw_inst.cpp
View file

@ -562,7 +562,7 @@ brw_inst::size_read(const struct intel_device_info *devinfo, int arg) const
case SHADER_OPCODE_LSC_FILL:
if (arg == FILL_SRC_PAYLOAD1) {
return lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32,
return brw_lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32,
as_scratch()->use_transpose ? 1 : exec_size) *
REG_SIZE;
}
@ -572,7 +572,7 @@ brw_inst::size_read(const struct intel_device_info *devinfo, int arg) const
if (arg == SPILL_SRC_PAYLOAD1) {
assert(!as_scratch()->use_transpose);
return lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32, exec_size) *
return brw_lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32, exec_size) *
REG_SIZE;
} else if (arg == SPILL_SRC_PAYLOAD2) {
return src[arg].component_size(exec_size);

6
src/intel/compiler/brw/brw_lower_fill_spill.cpp
View file

@ -77,11 +77,11 @@ brw_lower_lsc_fill(const intel_device_info *devinfo, brw_shader &s,
unspill_inst->sfid = BRW_SFID_UGM;
unspill_inst->header_size = 0;
unspill_inst->mlen = lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32,
unspill_inst->mlen = brw_lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32,
unspill_inst->exec_size);
unspill_inst->ex_mlen = 0;
unspill_inst->size_written =
lsc_msg_dest_len(devinfo, LSC_DATA_SIZE_D32, bld.dispatch_width()) * REG_SIZE;
brw_lsc_msg_dest_len(devinfo, LSC_DATA_SIZE_D32, bld.dispatch_width()) * REG_SIZE;
unspill_inst->has_side_effects = false;
unspill_inst->is_volatile = true;
unspill_inst->bindless_surface = true;
@ -131,7 +131,7 @@ brw_lower_lsc_spill(const intel_device_info *devinfo, brw_inst *inst)
false /* transpose */,
LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS));
spill_inst->header_size = 0;
spill_inst->mlen = lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32,
spill_inst->mlen = brw_lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32,
bld.dispatch_width());
spill_inst->ex_mlen = reg_size;
spill_inst->size_written = 0;

17
src/intel/compiler/brw/brw_lower_logical_sends.cpp
View file

@ -107,7 +107,7 @@ lower_urb_read_logical_send_xe2(const brw_builder &bld, brw_urb_inst *urb)
LSC_CACHE(devinfo, LOAD, L1UC_L3UC));
send->mlen = lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32, send->exec_size);
send->mlen = brw_lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32, send->exec_size);
send->ex_mlen = 0;
send->header_size = 0;
send->has_side_effects = true;
@ -238,7 +238,7 @@ lower_urb_write_logical_send_xe2(const brw_builder &bld, brw_urb_inst *urb)
setup_lsc_surface_descriptors(bld, send, send->desc, brw_reg(), offset);
send->mlen = lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32, send->exec_size);
send->mlen = brw_lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32, send->exec_size);
send->ex_mlen = ex_mlen;
send->header_size = 0;
send->has_side_effects = true;
@ -1339,7 +1339,7 @@ lower_lsc_memory_logical_send(const brw_builder &bld, brw_mem_inst *mem)
setup_lsc_surface_descriptors(bld, send, send->desc, binding, base_offset);
send->mlen = lsc_msg_addr_len(devinfo, addr_size,
send->mlen = brw_lsc_msg_addr_len(devinfo, addr_size,
send->exec_size * coord_components);
send->ex_mlen = ex_mlen;
send->header_size = 0;
@ -1537,7 +1537,7 @@ lower_hdc_memory_logical_send(const brw_builder &bld, brw_mem_inst *mem)
if (lsc_opcode_is_atomic(op)) {
desc = brw_dp_typed_atomic_desc(devinfo, mem->exec_size, mem->group,
lsc_op_to_legacy_atomic(op),
brw_lsc_op_to_legacy_atomic(op),
has_dest);
} else {
desc = brw_dp_typed_surface_rw_desc(devinfo, mem->exec_size,
@ -1554,7 +1554,7 @@ lower_hdc_memory_logical_send(const brw_builder &bld, brw_mem_inst *mem)
sfid = BRW_SFID_HDC1;
if (lsc_opcode_is_atomic(op)) {
unsigned aop = lsc_op_to_legacy_atomic(op);
unsigned aop = brw_lsc_op_to_legacy_atomic(op);
if (lsc_opcode_is_atomic_float(op)) {
desc = brw_dp_a64_untyped_atomic_float_desc(devinfo, mem->exec_size,
data_bit_size, aop,
@ -1580,7 +1580,7 @@ lower_hdc_memory_logical_send(const brw_builder &bld, brw_mem_inst *mem)
sfid = surface_access ? BRW_SFID_HDC1 : BRW_SFID_HDC0;
if (lsc_opcode_is_atomic(op)) {
unsigned aop = lsc_op_to_legacy_atomic(op);
unsigned aop = brw_lsc_op_to_legacy_atomic(op);
if (lsc_opcode_is_atomic_float(op)) {
desc = brw_dp_untyped_atomic_float_desc(devinfo, mem->exec_size,
aop, has_dest);
@ -1702,7 +1702,7 @@ lower_lsc_varying_pull_constant_logical_send(const brw_builder &bld,
alignment >= 4 ? 4 : 1 /* num_channels */,
false /* transpose */,
LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS));
send->mlen = lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32, send->exec_size);
send->mlen = brw_lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32, send->exec_size);
setup_lsc_surface_descriptors(bld, send, send->desc, binding, 0);
@ -2415,8 +2415,7 @@ brw_lower_uniform_pull_constant_loads(brw_shader &s)
send->size_written / 4,
true /* transpose */,
LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS));
send->mlen = lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32, 1);
send->mlen = brw_lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32, 1);
send->ex_mlen = 0;
send->header_size = 0;
send->has_side_effects = false;

2
src/intel/compiler/brw/brw_reg_allocate.cpp
View file

@ -879,7 +879,7 @@ brw_reg_alloc::emit_unspill(const brw_builder &bld,
unspill_inst->offset = spill_offset;
unspill_inst->use_transpose = use_transpose;
unspill_inst->size_written =
lsc_msg_dest_len(devinfo, LSC_DATA_SIZE_D32, bld.dispatch_width()) * REG_SIZE;
brw_lsc_msg_dest_len(devinfo, LSC_DATA_SIZE_D32, bld.dispatch_width()) * REG_SIZE;
assert(unspill_inst->size_written == (reg_size * REG_SIZE));
_mesa_set_add(spill_insts, unspill_inst);