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aco: implement 16-bit nir_op_ftrunc/nir_op_fround_even

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
This commit is contained in:
Samuel Pitoiset 2020-04-03 11:19:52 +02:00
parent ee96181ad9
commit 26ed9fb79e
1 changed files with 13 additions and 7 deletions
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20
src/amd/compiler/aco_instruction_selection.cpp
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@ -1909,10 +1909,14 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
break; break;
} }
case nir_op_ftrunc: { case nir_op_ftrunc: {
if (dst.size() == 1) { Temp src = get_alu_src(ctx, instr->src[0]);
if (dst.regClass() == v2b) {
Temp tmp = bld.vop1(aco_opcode::v_trunc_f16, bld.def(v1), src);
bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v2b), tmp);
} else if (dst.regClass() == v1) {
emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst); emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
} else if (dst.size() == 2) { } else if (dst.regClass() == v2) {
emit_trunc_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0])); emit_trunc_f64(ctx, bld, Definition(dst), src);
} else { } else {
fprintf(stderr, "Unimplemented NIR instr bit size: "); fprintf(stderr, "Unimplemented NIR instr bit size: ");
nir_print_instr(&instr->instr, stderr); nir_print_instr(&instr->instr, stderr);
@ -1921,15 +1925,17 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
break; break;
} }
case nir_op_fround_even: { case nir_op_fround_even: {
if (dst.size() == 1) { Temp src0 = get_alu_src(ctx, instr->src[0]);
if (dst.regClass() == v2b) {
Temp tmp = bld.vop1(aco_opcode::v_rndne_f16, bld.def(v1), src0);
bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v2b), tmp);
} else if (dst.regClass() == v1) {
emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst); emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
} else if (dst.size() == 2) { } else if (dst.regClass() == v2) {
if (ctx->options->chip_class >= GFX7) { if (ctx->options->chip_class >= GFX7) {
emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst); emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
} else { } else {
/* GFX6 doesn't support V_RNDNE_F64, lower it. */ /* GFX6 doesn't support V_RNDNE_F64, lower it. */
Temp src0 = get_alu_src(ctx, instr->src[0]);
Temp src0_lo = bld.tmp(v1), src0_hi = bld.tmp(v1); Temp src0_lo = bld.tmp(v1), src0_hi = bld.tmp(v1);
bld.pseudo(aco_opcode::p_split_vector, Definition(src0_lo), Definition(src0_hi), src0); bld.pseudo(aco_opcode::p_split_vector, Definition(src0_lo), Definition(src0_hi), src0);