nir: add a new push_data_intel intrinsic

We're finally moving on from misusing various intrinsics :
  - load_uniform
  - load_push_constant
  - load_ubo*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38975>

src/compiler/nir/nir_divergence_analysis.c

@@ -364,6 +364,12 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
       is_divergent = false;
       break;
 
+   case nir_intrinsic_load_push_data_intel:
+      is_divergent =
+         (nir_intrinsic_access(instr) & ACCESS_NON_UNIFORM) &&
+         src_divergent(instr->src[0], state);
+      break;
+
    case nir_intrinsic_load_ubo_uniform_block_intel:
    case nir_intrinsic_load_ssbo_uniform_block_intel:
    case nir_intrinsic_load_shared_uniform_block_intel:

src/compiler/nir/nir_intrinsics.py

@@ -2563,6 +2563,14 @@ load("urb_input_handle_indexed_intel", [1], [], [CAN_ELIMINATE, CAN_REORDER])
 # Inline register delivery (available on Gfx12.5+ for CS/Mesh/Task stages)
 load("inline_data_intel", [], [BASE], [CAN_ELIMINATE, CAN_REORDER])
 
+# Load push data on Intel VS,TCS,TES,GS,FS stages
+# src[] = { offset }
+#
+# We use the ACCESS index mostly for ACCESS_NON_UNIFORM, this allows us to
+# preserve the semantic of load_push_constant which is always uniform
+# regardless of the offset source.
+load("push_data_intel", [1], [BASE, RANGE, ACCESS], [CAN_ELIMINATE, CAN_REORDER])
+
 # Dynamic tesselation parameters (see intel_tess_config).
 system_value("tess_config_intel", 1)
 

src/compiler/nir/nir_lower_io.c

@@ -1006,6 +1006,7 @@ nir_get_io_offset_src_number(const nir_intrinsic_instr *instr)
    case nir_intrinsic_load_shared2_amd:
    case nir_intrinsic_load_const_ir3:
    case nir_intrinsic_load_shared_ir3:
+   case nir_intrinsic_load_push_data_intel:
       return 0;
    case nir_intrinsic_load_ubo:
    case nir_intrinsic_load_ubo_vec4:

src/compiler/nir/nir_lower_mem_access_bit_sizes.c

@@ -496,6 +496,7 @@ intrin_to_variable_mode(nir_intrinsic_op intrin)
       return nir_var_mem_ubo;
 
    case nir_intrinsic_load_push_constant:
+   case nir_intrinsic_load_push_data_intel:
       return nir_var_mem_push_const;
 
    case nir_intrinsic_load_global:

src/compiler/nir/nir_lower_shader_calls.c

@@ -114,6 +114,7 @@ can_remat_instr(nir_instr *instr, struct u_sparse_bitset *remat)
       case nir_intrinsic_load_vulkan_descriptor:
       case nir_intrinsic_load_push_constant:
       case nir_intrinsic_load_global_constant:
+      case nir_intrinsic_load_push_data_intel:
          /* These intrinsics don't need to be spilled as long as they don't
           * depend on any spilled values.
           */

src/compiler/nir/nir_opt_call.c

@@ -32,6 +32,7 @@ can_remat_instr(nir_instr *instr)
       case nir_intrinsic_load_global_constant:
       case nir_intrinsic_load_scalar_arg_amd:
       case nir_intrinsic_load_vector_arg_amd:
+      case nir_intrinsic_load_push_data_intel:
          return true;
       case nir_intrinsic_load_global:
       case nir_intrinsic_load_global_amd:

src/compiler/nir/nir_opt_gcm.c

@@ -273,7 +273,8 @@ pin_intrinsic(nir_intrinsic_instr *intrin)
                                nir_var_mem_ubo | nir_var_mem_ssbo)))) {
       if (!is_binding_uniform(intrin->src[0]))
          instr->pass_flags = GCM_INSTR_PINNED;
-   } else if (intrin->intrinsic == nir_intrinsic_load_push_constant) {
+   } else if (intrin->intrinsic == nir_intrinsic_load_push_constant ||
+              intrin->intrinsic == nir_intrinsic_load_push_data_intel) {
       if (!nir_src_is_always_uniform(intrin->src[0]))
          instr->pass_flags = GCM_INSTR_PINNED;
    } else if (intrin->intrinsic == nir_intrinsic_load_deref &&

src/compiler/nir/nir_opt_peephole_select.c

@@ -203,6 +203,7 @@ block_check_for_allowed_instrs(nir_block *block, unsigned *count,
          case nir_intrinsic_ballot:
          case nir_intrinsic_ballot_relaxed:
          case nir_intrinsic_mbcnt_amd:
+         case nir_intrinsic_load_push_data_intel:
             if (!alu_ok)
                return false;
             break;

src/compiler/nir/nir_opt_preamble.c

@@ -180,6 +180,7 @@ can_move_intrinsic(nir_intrinsic_instr *instr, opt_preamble_ctx *ctx)
    case nir_intrinsic_load_cull_any_enabled_amd:
    case nir_intrinsic_load_cull_small_triangle_precision_amd:
    case nir_intrinsic_load_vbo_base_agx:
+   case nir_intrinsic_load_push_data_intel:
       return true;
 
    /* Intrinsics which can be moved depending on hardware */

src/compiler/nir/nir_opt_shrink_vectors.c

@@ -370,6 +370,7 @@ opt_shrink_vectors_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
    case nir_intrinsic_load_ssbo:
    case nir_intrinsic_load_ssbo_intel:
    case nir_intrinsic_load_push_constant:
+   case nir_intrinsic_load_push_data_intel:
    case nir_intrinsic_load_constant:
    case nir_intrinsic_load_shared:
    case nir_intrinsic_load_global: