From 269d2c4a3f570d7bf92e7df13b42b5f7b7468dbd Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Fri, 9 Feb 2024 10:51:20 -0800 Subject: [PATCH] intel/compiler: Enable packing of offset with LOD or Bias Move intel_nir_lower_texture just before nir_lower_tex since we need to operate on the offset and those are getting lowerd. v2: (Ian) - Rename variable name to intel_tex_options Reviewed-by: Ian Romanick Signed-off-by: Sagar Ghuge Part-of: --- src/intel/compiler/brw_nir.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 203113ed3ec..122c862b9c1 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -930,6 +930,11 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, if (intel_needs_workaround(devinfo, 1806565034) && !opts->robust_image_access) OPT(intel_nir_clamp_image_1d_2d_array_sizes); + const struct intel_nir_lower_texture_opts intel_tex_options = { + .combined_lod_or_bias_and_offset = compiler->devinfo->ver >= 20, + }; + OPT(intel_nir_lower_texture, &intel_tex_options); + const nir_lower_tex_options tex_options = { .lower_txp = ~0, .lower_txf_offset = true, @@ -953,8 +958,11 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, * rerun the pass because the instructions inserted by the first lowering * are not visible during that first pass. */ - if (OPT(nir_lower_tex, &tex_options)) + if (OPT(nir_lower_tex, &tex_options)) { + OPT(intel_nir_lower_texture, &intel_tex_options); OPT(nir_lower_tex, &tex_options); + } + OPT(nir_normalize_cubemap_coords); OPT(nir_lower_global_vars_to_local);