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a4xx: add some better documentation for compute registers

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These were driven by seeing 0x1c (and other) values set by blob, as well
as comparing to equivalent a3xx documentation.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12784>
This commit is contained in:
Ilia Mirkin 2021-09-08 21:37:06 -04:00 • committed by Marge Bot
parent 5f66e5e56d
commit 269cbc8a4d
1 changed files with 14 additions and 5 deletions
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19
src/freedreno/registers/adreno/a4xx.xml
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@ -1670,7 +1670,7 @@ perhaps they should be taken with a grain of salt
<bitfield name="COLOR_SRGB" pos="18" type="boolean"/>
</reg32>
</array>
<reg32 offset="0x2300" name="SP_CS_CTRL_REG0"/>
<reg32 offset="0x2300" name="SP_CS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
<reg32 offset="0x2301" name="SP_CS_OBJ_OFFSET_REG"/>
<reg32 offset="0x2302" name="SP_CS_OBJ_START"/>
<reg32 offset="0x2303" name="SP_CS_PVT_MEM_PARAM"/>
@ -2097,15 +2097,24 @@ perhaps they should be taken with a grain of salt
</reg32>
<reg32 offset="0x23d3" name="HLSQ_CL_NDRANGE_6"/>
<reg32 offset="0x23d4" name="HLSQ_CL_CONTROL_0">
<bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
<bitfield name="WGIDCONSTID" low="0" high="11" type="a3xx_regid"/>
<bitfield name="UNK12CONSTID" low="12" high="23" type="a3xx_regid"/>
<bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
</reg32>
<reg32 offset="0x23d5" name="HLSQ_CL_CONTROL_1"/>
<reg32 offset="0x23d6" name="HLSQ_CL_KERNEL_CONST"/>
<reg32 offset="0x23d5" name="HLSQ_CL_CONTROL_1">
<bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
<bitfield name="UNK12CONSTID" low="12" high="23" type="a3xx_regid"/>
</reg32>
<reg32 offset="0x23d6" name="HLSQ_CL_KERNEL_CONST">
<bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
<bitfield name="NUMWGCONSTID" low="12" high="23" type="a3xx_regid"/>
</reg32>
<reg32 offset="0x23d7" name="HLSQ_CL_KERNEL_GROUP_X"/>
<reg32 offset="0x23d8" name="HLSQ_CL_KERNEL_GROUP_Y"/>
<reg32 offset="0x23d9" name="HLSQ_CL_KERNEL_GROUP_Z"/>
<reg32 offset="0x23da" name="HLSQ_CL_WG_OFFSET"/>
<reg32 offset="0x23da" name="HLSQ_CL_WG_OFFSET">
<bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
</reg32>
<reg32 offset="0x23db" name="HLSQ_UPDATE_CONTROL"/>
<!-- PC registers -->