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i965/fs: Allow spilling for SIMD16 compute shaders
For fragment shaders, we can always use a SIMD8 program. Therefore, if
we detect spilling with a SIMD16 program, then it is better to skip
generating a SIMD16 program to only rely on a SIMD8 program.
Unfortunately, this doesn't work for compute shaders. For a compute
shader, we may be required to use SIMD16 if the local workgroup size
is bigger than a certain size. For example, on gen7, if the local
workgroup size is larger than 512, then a SIMD16 program is required.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93840
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit e1d54b1ba5)
This commit is contained in:
parent
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3 changed files with 14 additions and 1 deletions
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@ -5228,7 +5228,7 @@ fs_visitor::allocate_registers()
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* SIMD8. There's probably actually some intermediate point where
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* SIMD16 with a couple of spills is still better.
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*/
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if (dispatch_width == 16) {
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if (dispatch_width == 16 && min_dispatch_width <= 8) {
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fail("Failure to register allocate. Reduce number of "
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"live scalar values to avoid this.");
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} else {
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@ -407,6 +407,7 @@ public:
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bool spilled_any_registers;
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const unsigned dispatch_width; /**< 8 or 16 */
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unsigned min_dispatch_width;
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int shader_time_index;
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@ -1021,6 +1021,18 @@ fs_visitor::init()
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unreachable("unhandled shader stage");
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}
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if (stage == MESA_SHADER_COMPUTE) {
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const brw_cs_prog_data *cs_prog_data =
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(const brw_cs_prog_data *) prog_data;
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unsigned size = cs_prog_data->local_size[0] *
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cs_prog_data->local_size[1] *
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cs_prog_data->local_size[2];
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size = DIV_ROUND_UP(size, devinfo->max_cs_threads);
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min_dispatch_width = size > 16 ? 32 : (size > 8 ? 16 : 8);
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} else {
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min_dispatch_width = 8;
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}
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this->prog_data = this->stage_prog_data;
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this->failed = false;
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