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i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on Skylake.

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Skylake introduces a new base address for a feature we don't yet expose.
Setting these to 0 should be safe.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
This commit is contained in:
Kenneth Graunke 2014-04-21 19:38:18 -07:00
parent eaf12022d2
commit 263b584d5e
1 changed files with 11 additions and 2 deletions
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13
src/mesa/drivers/dri/i965/gen8_misc_state.c
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@ -31,8 +31,12 @@
*/ */
static void upload_state_base_address(struct brw_context *brw) static void upload_state_base_address(struct brw_context *brw)
{ {
BEGIN_BATCH(16); perf_debug("Missing MOCS setup for STATE_BASE_ADDRESS.");
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (16 - 2));
int pkt_len = brw->gen >= 9 ? 19 : 16;
BEGIN_BATCH(pkt_len);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (pkt_len - 2));
/* General state base address: stateless DP read/write requests */ /* General state base address: stateless DP read/write requests */
OUT_BATCH(BDW_MOCS_WB << 4 | 1); OUT_BATCH(BDW_MOCS_WB << 4 | 1);
OUT_BATCH(0); OUT_BATCH(0);
@ -59,6 +63,11 @@ static void upload_state_base_address(struct brw_context *brw)
OUT_BATCH(0xfffff001); OUT_BATCH(0xfffff001);
/* Instruction access upper bound */ /* Instruction access upper bound */
OUT_BATCH(ALIGN(brw->cache.bo->size, 4096) | 1); OUT_BATCH(ALIGN(brw->cache.bo->size, 4096) | 1);
if (brw->gen >= 9) {
OUT_BATCH(1);
OUT_BATCH(0);
OUT_BATCH(0);
}
ADVANCE_BATCH(); ADVANCE_BATCH();
brw->state.dirty.brw |= BRW_NEW_STATE_BASE_ADDRESS; brw->state.dirty.brw |= BRW_NEW_STATE_BASE_ADDRESS;