diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index 6b4504feeef..bab51f46549 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -2672,7 +2672,7 @@ agx_dump_stats(agx_context *ctx, unsigned size, char **out)
       "%u uniforms, %u scratch, %u threads, %u loops, "
       "%u:%u spills:fills",
       gl_shader_stage_name(ctx->stage), nr_ins, cycles.alu, cycles.f_scib,
-      cycles.ic, size, ctx->max_reg, ctx->out->push_count, ctx->scratch_size,
+      cycles.ic, size, ctx->max_reg, ctx->out->push_count, ctx->scratch_size_B,
       nr_threads, ctx->loop_count, spills, fills);
 }
 
@@ -3225,7 +3225,7 @@ agx_compile_function_nir(nir_shader *nir, nir_function_impl *impl,
     */
    if (ctx->any_scratch) {
       assert(!ctx->is_preamble && "preambles don't use scratch");
-      ctx->scratch_size = ALIGN(nir->scratch_size, 16);
+      ctx->scratch_size_B = ALIGN(nir->scratch_size, 16);
    }
 
    /* Stop the main shader or preamble shader after the exit block. For real
@@ -3284,9 +3284,9 @@ agx_compile_function_nir(nir_shader *nir, nir_function_impl *impl,
    agx_validate(ctx, "RA");
    agx_lower_64bit_postra(ctx);
 
-   if (ctx->scratch_size > 0) {
+   if (ctx->scratch_size_B > 0) {
       /* Apple always allocate 40 more bytes in the entrypoint and align to 4. */
-      uint64_t stack_size = ALIGN(DIV_ROUND_UP(ctx->scratch_size, 4) + 10, 4);
+      uint64_t stack_size = ALIGN(DIV_ROUND_UP(ctx->scratch_size_B, 4) + 10, 4);
 
       assert(stack_size < INT16_MAX);
 
@@ -3344,7 +3344,7 @@ agx_compile_function_nir(nir_shader *nir, nir_function_impl *impl,
     * GPRs. Do it here so the driver doesn't have to worry about it.
     */
    if (impl->function->is_preamble)
-      out->nr_preamble_gprs = ctx->scratch_size ? 256 : nr_gprs;
+      out->nr_preamble_gprs = ctx->scratch_size_B ? 256 : nr_gprs;
    else
       out->nr_gprs = nr_gprs;
 
diff --git a/src/asahi/compiler/agx_compiler.h b/src/asahi/compiler/agx_compiler.h
index 32b6b5f2d7e..317c5c77e8c 100644
--- a/src/asahi/compiler/agx_compiler.h
+++ b/src/asahi/compiler/agx_compiler.h
@@ -442,7 +442,7 @@ typedef struct {
    nir_shader *nir;
    gl_shader_stage stage;
    bool is_preamble;
-   unsigned scratch_size;
+   unsigned scratch_size_B;
 
    struct list_head blocks; /* list of agx_block */
    struct agx_shader_info *out;
@@ -498,7 +498,7 @@ typedef struct {
    /* Beginning of our stack allocation used for spilling, below that is
     * NIR-level scratch.
     */
-   unsigned spill_base;
+   unsigned spill_base_B;
 
    /* Beginning of stack allocation used for parallel copy lowering */
    bool has_spill_pcopy_reserved;
diff --git a/src/asahi/compiler/agx_lower_spill.c b/src/asahi/compiler/agx_lower_spill.c
index b865f4bf0cf..9cbdb9d5250 100644
--- a/src/asahi/compiler/agx_lower_spill.c
+++ b/src/asahi/compiler/agx_lower_spill.c
@@ -39,7 +39,7 @@ spill_fill(agx_builder *b, agx_instr *I, enum agx_size size, unsigned channels,
    }
 
    /* Calculate stack offset in bytes. IR registers are 2-bytes each. */
-   unsigned stack_offs_B = b->shader->spill_base + (mem.value * 2) + offset_B;
+   unsigned stack_offs_B = b->shader->spill_base_B + (mem.value * 2) + offset_B;
 
    /* Emit the spill/fill */
    if (I->dest[0].memory) {
diff --git a/src/asahi/compiler/agx_register_allocate.c b/src/asahi/compiler/agx_register_allocate.c
index b42ad30256e..c27d237449c 100644
--- a/src/asahi/compiler/agx_register_allocate.c
+++ b/src/asahi/compiler/agx_register_allocate.c
@@ -1497,8 +1497,8 @@ agx_ra(agx_context *ctx)
    }
 
    if (spilling) {
-      ctx->spill_base = ctx->scratch_size;
-      ctx->scratch_size += (max_mem_slot + 1) * 2;
+      ctx->spill_base_B = ctx->scratch_size_B;
+      ctx->scratch_size_B += (max_mem_slot + 1) * 2;
    }
 
    /* Vertex shaders preload the vertex/instance IDs (r5, r6) even if the shader