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i965/miptree: Refactor intel_miptree_resolve_color

Browse source 
The new version now takes a range of levels as well as a range of
layers.  It should also be a tiny bit faster because it only walks the
resolve_map list once instead of once per layer.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
This commit is contained in:
Jason Ekstrand 2017-05-22 09:23:45 -07:00
parent 64b829244b
commit 25d00e72e4
6 changed files with 35 additions and 38 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/mesa/drivers/dri/i965/brw_blorp.c
View file

@ -177,7 +177,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
flags |= INTEL_MIPTREE_IGNORE_CCS_E;
intel_miptree_resolve_color(brw, mt,
*level, start_layer, num_layers, flags);
*level, 1,
start_layer, num_layers, flags);
assert(!intel_miptree_has_color_unresolved(mt, *level, 1,
start_layer, num_layers));

9
src/mesa/drivers/dri/i965/brw_context.c
View file

@ -318,9 +318,10 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
intel_renderbuffer(fb->_ColorDrawBuffers[i]);
if (irb &&
intel_miptree_resolve_color(
brw, irb->mt, irb->mt_level, irb->mt_layer, irb->layer_count,
INTEL_MIPTREE_IGNORE_CCS_E))
intel_miptree_resolve_color(brw, irb->mt,
irb->mt_level, 1,
irb->mt_layer, irb->layer_count,
INTEL_MIPTREE_IGNORE_CCS_E))
brw_render_cache_set_check_flush(brw, irb->mt->bo);
}
}
@ -1380,7 +1381,7 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
if (rb->mt->num_samples <= 1) {
assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
rb->layer_count == 1);
intel_miptree_resolve_color(brw, rb->mt, 0, 0, 1, 0);
intel_miptree_resolve_color(brw, rb->mt, 0, 1, 0, 1, 0);
} else {
intel_renderbuffer_downsample(brw, rb);
}

2
src/mesa/drivers/dri/i965/brw_draw.c
View file

@ -422,7 +422,7 @@ brw_predraw_set_aux_buffers(struct brw_context *brw)
!intel_miptree_is_lossless_compressed(brw, irb->mt)) {
assert(brw->gen >= 8);
intel_miptree_resolve_color(brw, irb->mt, irb->mt_level,
intel_miptree_resolve_color(brw, irb->mt, irb->mt_level, 1,
irb->mt_layer, irb->layer_count, 0);
}
}

8
src/mesa/drivers/dri/i965/intel_blit.c
View file

@ -326,8 +326,8 @@ intel_miptree_blit(struct brw_context *brw,
*/
intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
intel_miptree_resolve_color(brw, src_mt, src_level, src_slice, 1, 0);
intel_miptree_resolve_color(brw, dst_mt, dst_level, dst_slice, 1, 0);
intel_miptree_resolve_color(brw, src_mt, src_level, 1, src_slice, 1, 0);
intel_miptree_resolve_color(brw, dst_mt, dst_level, 1, dst_slice, 1, 0);
intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_slice);
if (src_flip)
@ -385,8 +385,8 @@ intel_miptree_copy(struct brw_context *brw,
*/
intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
intel_miptree_resolve_color(brw, src_mt, src_level, src_slice, 1, 0);
intel_miptree_resolve_color(brw, dst_mt, dst_level, dst_slice, 1, 0);
intel_miptree_resolve_color(brw, src_mt, src_level, 1, src_slice, 1, 0);
intel_miptree_resolve_color(brw, dst_mt, dst_level, 1, dst_slice, 1, 0);
intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_slice);
uint32_t src_image_x, src_image_y;

46
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View file

@ -2164,33 +2164,35 @@ intel_miptree_needs_color_resolve(const struct brw_context *brw,
bool
intel_miptree_resolve_color(struct brw_context *brw,
struct intel_mipmap_tree *mt, unsigned level,
unsigned start_layer, unsigned num_layers,
struct intel_mipmap_tree *mt,
uint32_t start_level, uint32_t num_levels,
uint32_t start_layer, uint32_t num_layers,
int flags)
{
intel_miptree_check_color_resolve(brw, mt, level, start_layer);
intel_miptree_check_color_resolve(brw, mt, start_level, start_layer);
if (!intel_miptree_needs_color_resolve(brw, mt, flags))
return false;
/* Arrayed fast clear is only supported for gen8+. */
assert(brw->gen >= 8 || num_layers == 1);
bool resolved = false;
for (unsigned i = 0; i < num_layers; ++i) {
intel_miptree_check_level_layer(mt, level, start_layer + i);
foreach_list_typed_safe(struct intel_resolve_map, map, link,
&mt->color_resolve_map) {
if (map->level < start_level ||
map->level >= (start_level + num_levels) ||
map->layer < start_layer ||
map->layer >= (start_layer + num_layers))
continue;
struct intel_resolve_map *item =
intel_resolve_map_get(&mt->color_resolve_map, level,
start_layer + i);
/* Arrayed and mip-mapped fast clear is only supported for gen8+. */
assert(brw->gen >= 8 || (map->level == 0 && map->layer == 0));
if (item) {
assert(item->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED);
intel_miptree_check_level_layer(mt, map->level, map->layer);
brw_blorp_resolve_color(brw, mt, level, start_layer);
intel_resolve_map_remove(item);
resolved = true;
}
assert(map->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED);
brw_blorp_resolve_color(brw, mt, map->level, map->layer);
intel_resolve_map_remove(map);
resolved = true;
}
return resolved;
@ -2201,16 +2203,8 @@ intel_miptree_all_slices_resolve_color(struct brw_context *brw,
struct intel_mipmap_tree *mt,
int flags)
{
if (!intel_miptree_needs_color_resolve(brw, mt, flags))
return;
foreach_list_typed_safe(struct intel_resolve_map, map, link,
&mt->color_resolve_map) {
assert(map->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED);
brw_blorp_resolve_color(brw, mt, map->level, map->layer);
intel_resolve_map_remove(map);
}
intel_miptree_resolve_color(brw, mt, 0, UINT32_MAX, 0, UINT32_MAX, flags);
}
/**

5
src/mesa/drivers/dri/i965/intel_mipmap_tree.h
View file

@ -937,8 +937,9 @@ intel_miptree_used_for_rendering(const struct brw_context *brw,
bool
intel_miptree_resolve_color(struct brw_context *brw,
struct intel_mipmap_tree *mt, unsigned level,
unsigned start_layer, unsigned num_layers,
struct intel_mipmap_tree *mt,
uint32_t start_level, uint32_t num_levels,
uint32_t start_layer, uint32_t num_layers,
int flags);
void