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i965/vs: Move the other two src_reg/dst_reg constructors to brw_vec4.cpp.

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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Eric Anholt 2012-07-04 13:31:46 -07:00
parent b2f5d4c3ec
commit 25ca9cc823
2 changed files with 43 additions and 43 deletions
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43
src/mesa/drivers/dri/i965/brw_vec4.cpp
View file

@ -104,6 +104,36 @@ src_reg::src_reg(int32_t i)
this->imm.i = i;
}
src_reg::src_reg(dst_reg reg)
{
init();
this->file = reg.file;
this->reg = reg.reg;
this->reg_offset = reg.reg_offset;
this->type = reg.type;
this->reladdr = reg.reladdr;
this->fixed_hw_reg = reg.fixed_hw_reg;
int swizzles[4];
int next_chan = 0;
int last = 0;
for (int i = 0; i < 4; i++) {
if (!(reg.writemask & (1 << i)))
continue;
swizzles[next_chan++] = last = i;
}
for (; next_chan < 4; next_chan++) {
swizzles[next_chan] = last;
}
this->swizzle = BRW_SWIZZLE4(swizzles[0], swizzles[1],
swizzles[2], swizzles[3]);
}
bool
vec4_instruction::is_tex()
{
@ -154,6 +184,19 @@ dst_reg::dst_reg(struct brw_reg reg)
this->fixed_hw_reg = reg;
}
dst_reg::dst_reg(src_reg reg)
{
init();
this->file = reg.file;
this->reg = reg.reg;
this->reg_offset = reg.reg_offset;
this->type = reg.type;
this->writemask = WRITEMASK_XYZW;
this->reladdr = reg.reladdr;
this->fixed_hw_reg = reg.fixed_hw_reg;
}
bool
vec4_instruction::is_math()
{

43
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
View file

@ -30,49 +30,6 @@ extern "C" {
namespace brw {
src_reg::src_reg(dst_reg reg)
{
init();
this->file = reg.file;
this->reg = reg.reg;
this->reg_offset = reg.reg_offset;
this->type = reg.type;
this->reladdr = reg.reladdr;
this->fixed_hw_reg = reg.fixed_hw_reg;
int swizzles[4];
int next_chan = 0;
int last = 0;
for (int i = 0; i < 4; i++) {
if (!(reg.writemask & (1 << i)))
continue;
swizzles[next_chan++] = last = i;
}
for (; next_chan < 4; next_chan++) {
swizzles[next_chan] = last;
}
this->swizzle = BRW_SWIZZLE4(swizzles[0], swizzles[1],
swizzles[2], swizzles[3]);
}
dst_reg::dst_reg(src_reg reg)
{
init();
this->file = reg.file;
this->reg = reg.reg;
this->reg_offset = reg.reg_offset;
this->type = reg.type;
this->writemask = WRITEMASK_XYZW;
this->reladdr = reg.reladdr;
this->fixed_hw_reg = reg.fixed_hw_reg;
}
vec4_instruction::vec4_instruction(vec4_visitor *v,
enum opcode opcode, dst_reg dst,
src_reg src0, src_reg src1, src_reg src2)