From 25836895f3d57dbfd4d13572c4bb8f2ea5938408 Mon Sep 17 00:00:00 2001 From: Emma Anholt Date: Sat, 2 Apr 2022 22:19:59 -0700 Subject: [PATCH] r600: Fix reading back from a temp array immediately after writing on RV770. KHR-GL33.shaders.indexing.tmp_array.vertexid regressed with the switch to NIR-to-TGSI because the shader got optimized enough to emit a read just after writing to the array (the kind of situation where a non-rel write would have been followed by a PV/PS read). The R600 and EG docs say you always need to do this, but apparently some hardware gives you the right answer anyway so we don't flag it on all of them. Reviewed-by: Gert Wollny Part-of: --- src/gallium/drivers/r600/r600_asm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c index 83bdfc75051..ec772d48dc1 100644 --- a/src/gallium/drivers/r600/r600_asm.c +++ b/src/gallium/drivers/r600/r600_asm.c @@ -148,6 +148,17 @@ void r600_bytecode_init(struct r600_bytecode *bc, if ((chip_class == R600) && (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) { bc->ar_handling = AR_HANDLE_RV6XX; + + /* Insert a nop after a relative temp write so that a read in + * the following instruction group gets the right value. The + * r600 and EG ISA specs both say that read-after-rel-write of a + * register in the next instr group is illegal, but apparently + * that's not true on all chips (see commit + * c96b9834032952492efbd2d1f5511fe225704918). + */ + bc->r6xx_nop_after_rel_dst = 1; + } else if (family == CHIP_RV770) { + bc->ar_handling = AR_HANDLE_NORMAL; bc->r6xx_nop_after_rel_dst = 1; } else { bc->ar_handling = AR_HANDLE_NORMAL;