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r300g: emit MSPOS regs

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This commit is contained in:
Marek Olšák 2010-04-26 06:29:10 +02:00
parent b9e637e8cf
commit 2579fe4044
6 changed files with 21 additions and 15 deletions
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14
src/gallium/drivers/r300/r300_state_invariant.c
View file

@ -43,15 +43,17 @@ void r300_emit_invariant_state(struct r300_context* r300,
{
CS_LOCALS(r300);
if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
/* Subpixel multisampling for AA. */
BEGIN_CS(4);
OUT_CS_REG(R300_GB_MSPOS0, 0x66666666);
OUT_CS_REG(R300_GB_MSPOS1, 0x6666666);
END_CS;
}
BEGIN_CS(12 + (r300->screen->caps.has_tcl ? 2 : 0));
/*** Graphics Backend (GB) ***/
/* Subpixel multisampling for AA
* These are commented out because glisse's CS checker doesn't like them.
* I presume these will be re-enabled later.
* OUT_CS_REG(R300_GB_MSPOS0, 0x66666666);
* OUT_CS_REG(R300_GB_MSPOS1, 0x6666666);
*/
/* Source of fog depth */
OUT_CS_REG(R300_GB_SELECT, R300_GB_FOG_SELECT_1_1_W);

4
src/gallium/drivers/r300/r300_texture.c
View file

@ -762,12 +762,12 @@ static unsigned r300_texture_get_nblocksy(struct r300_texture* tex,
static void r300_texture_3d_fix_mipmapping(struct r300_screen *screen,
struct r300_texture *tex)
{
/* The kernels <= 2.6.34-rc3 compute the size of mipmapped 3D textures
/* The kernels <= 2.6.34-rc4 compute the size of mipmapped 3D textures
* incorrectly. This is a workaround to prevent CS from being rejected. */
unsigned i, size;
if (screen->rws->get_value(screen->rws, R300_VID_TEX3D_MIP_BUG) &&
if (screen->rws->get_value(screen->rws, R300_VID_DRM_2_3_0) &&
tex->b.b.target == PIPE_TEXTURE_3D &&
tex->b.b.last_level > 0) {
size = 0;

2
src/gallium/drivers/r300/r300_winsys.h
View file

@ -39,7 +39,7 @@ enum r300_value_id {
R300_VID_GB_PIPES,
R300_VID_Z_PIPES,
R300_VID_SQUARE_TILING_SUPPORT,
R300_VID_TEX3D_MIP_BUG,
R300_VID_DRM_2_3_0,
};
enum r300_reference_domain { /* bitfield */

4
src/gallium/winsys/radeon/drm/radeon_drm.c
View file

@ -100,8 +100,8 @@ static void do_ioctls(int fd, struct radeon_libdrm_winsys* winsys)
version->version_minor >= 1;
#endif
/* XXX */
winsys->tex3d_mip_bug = TRUE;
winsys->drm_2_3_0 = version->version_major > 2 ||
version->version_minor >= 3;
info.request = RADEON_INFO_DEVICE_ID;
retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));

4
src/gallium/winsys/radeon/drm/radeon_r300.c
View file

@ -265,8 +265,8 @@ static uint32_t radeon_get_value(struct r300_winsys_screen *rws,
return ws->z_pipes;
case R300_VID_SQUARE_TILING_SUPPORT:
return ws->squaretiling;
case R300_VID_TEX3D_MIP_BUG:
return ws->tex3d_mip_bug;
case R300_VID_DRM_2_3_0:
return ws->drm_2_3_0;
}
return 0;
}

8
src/gallium/winsys/radeon/drm/radeon_winsys.h
View file

@ -60,8 +60,12 @@ struct radeon_libdrm_winsys {
/* Square tiling support. */
boolean squaretiling;
/* Square tiling support. */
boolean tex3d_mip_bug;
/* DRM 2.3.0
* - R500 VAP regs
* - MSPOS regs
* - Fixed texture 3D size calculation
*/
boolean drm_2_3_0;
/* DRM FD */
int fd;