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https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-09 02:28:10 +02:00
Improving Vladimirs alpha test fix a bit as it turns out r300Enable didnt correctly disable alpha test. Vertex programs with high vertex count now run a lot faster as software fallback is no longer on. Also disabling 'temp to result'-instructions as they probably violate the spec and dont seem to be something thats needed.
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0bd5373d94
commit
2579c32a5f
5 changed files with 15 additions and 19 deletions
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@ -634,7 +634,7 @@ void r300EmitWait(r300ContextPtr rmesa, GLuint flags)
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1 * sizeof(int),
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__FUNCTION__);
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cmd[0].i = 0;
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cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
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cmd[0].wait.cmd_type = R300_CMD_WAIT;
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cmd[0].wait.flags = flags;
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}
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}
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@ -117,7 +117,7 @@ static const struct tnl_pipeline_stage *r300_pipeline[] = {
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&_tnl_fog_coordinate_stage,
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&_tnl_texgen_stage,
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&_tnl_texture_transform_stage,
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&_tnl_vertex_program_stage,
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//&_tnl_vertex_program_stage,
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/* Try again to go to tcl?
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* - no good for asymmetric-twoside (do with multipass)
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@ -513,6 +513,7 @@ static void r300_render_vb_primitive(r300ContextPtr rmesa,
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}
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if(num_verts > 65535){ /* not implemented yet */
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WARN_ONCE("Too many elts\n");
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return;
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}
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r300EmitElts(ctx, rmesa->state.Elts+start, num_verts);
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@ -459,12 +459,12 @@ static void r300Enable(GLcontext* ctx, GLenum cap, GLboolean state)
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break;
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case GL_ALPHA_TEST:
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R200_STATECHANGE(r300, at);
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R300_STATECHANGE(r300, at);
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if (state) {
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r300->hw.at.cmd[R300_AT_ALPHA_TEST] |=
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R300_ALPHA_TEST_ENABLE;
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} else {
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r300->hw.at.cmd[R300_AT_ALPHA_TEST] |=
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r300->hw.at.cmd[R300_AT_ALPHA_TEST] &=
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~R300_ALPHA_TEST_ENABLE;
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}
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break;
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@ -1353,7 +1353,8 @@ void r300_setup_textures(GLcontext *ctx)
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}
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for(i=0; i < mtu; i++) {
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/*if(ctx->Texture.Unit[i].Enabled == 0)
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continue;*/
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if( ((r300->state.render_inputs & (_TNL_BIT_TEX0<<i))!=0) != ((ctx->Texture.Unit[i].Enabled)!=0) ) {
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WARN_ONCE("Mismatch between render_inputs and ctx->Texture.Unit[i].Enabled value.\n");
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}
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@ -1998,10 +1999,8 @@ void r300ResetHwState(r300ContextPtr r300)
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r300_set_blend_state(ctx);
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r300->hw.at.cmd[R300_AT_ALPHA_TEST] = 0;
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r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
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if(ctx->Color.AlphaEnabled)
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r300->hw.at.cmd[R300_AT_ALPHA_TEST] |= R300_ALPHA_TEST_ENABLE;
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r300Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
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/* Initialize magic registers
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TODO : learn what they really do, or get rid of
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@ -2171,10 +2170,6 @@ void r300ResetHwState(r300ContextPtr r300)
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r300->hw.unk4BC8.cmd[2] = 0;
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r300->hw.unk4BC8.cmd[3] = 0;
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//r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
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#if 0
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r300->hw.at.cmd[R300_AT_ALPHA_TEST] = 0;
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#endif
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r300->hw.at.cmd[R300_AT_UNKNOWN] = 0;
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r300->hw.unk4BD8.cmd[1] = 0;
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@ -492,7 +492,7 @@ static void translate_program(struct r300_vertex_program *vp)
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for(i=0; i < operands; i++)
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src[i]=vpi->SrcReg[i];
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#if 1
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if(operands == 3){ /* TODO: scalars */
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if( CMP_SRCS(src[1], src[2]) || CMP_SRCS(src[0], src[2]) ){
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o_inst->op=MAKE_VSF_OP(R300_VPI_OUT_OP_ADD, u_temp_i,
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@ -538,7 +538,7 @@ static void translate_program(struct r300_vertex_program *vp)
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u_temp_i--;
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}
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}
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#endif
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/* these ops need special handling.
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Ops that need temp vars should probably be given reg indexes starting at the end of tmp area. */
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switch(vpi->Opcode){
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@ -759,8 +759,8 @@ static void translate_program(struct r300_vertex_program *vp)
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exit(-1);
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break;
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}
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next:
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next: ;
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#if 0
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/* If instruction writes to result and one of the inputs is tmp, we move it at the end of program */
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if(vpi->DstReg.File == PROGRAM_OUTPUT){
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for(operand_index=0; operand_index < operands; operand_index++)
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@ -770,13 +770,13 @@ static void translate_program(struct r300_vertex_program *vp)
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break;
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}
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}
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#endif
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}
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#if 0
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/* Put "tmp to result" instructions in */
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for(i=0; i < vp->t2rs; i++, o_inst++)
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*o_inst=t2rs[i];
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#endif
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vp->program.length=(o_inst - vp->program.body.i) * 4;
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if(u_temp_i < vp->num_temporaries)
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