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aco/gfx11.5: select SALU fneg/fabs

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Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29245>
This commit is contained in:
Georg Lehmann 2023-09-22 11:38:35 +02:00 • committed by Marge Bot
parent 284b9965e8
commit 2549bc2f9e
2 changed files with 22 additions and 2 deletions
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20
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -2601,6 +2601,10 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand::c32(0x80000000u), upper);
bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
} else if (dst.regClass() == s1 && instr->def.bit_size == 16) {
bld.sop2(aco_opcode::s_mul_f16, Definition(dst), Operand::c16(0xbc00u), src);
} else if (dst.regClass() == s1 && instr->def.bit_size == 32) {
bld.sop2(aco_opcode::s_mul_f32, Definition(dst), Operand::c32(0xbf800000u), src);
} else {
isel_err(&instr->instr, "Unimplemented NIR instr bit size");
}
@ -2637,6 +2641,22 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand::c32(0x7FFFFFFFu), upper);
bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
} else if (dst.regClass() == s1 && instr->def.bit_size == 16) {
Temp mask = bld.copy(bld.def(s1), Operand::c32(0x7fff));
if (ctx->block->fp_mode.denorm16_64 == fp_denorm_keep) {
bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), mask, src);
} else {
Temp tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), mask, src);
bld.sop2(aco_opcode::s_mul_f16, Definition(dst), Operand::c16(0x3c00), tmp);
}
} else if (dst.regClass() == s1 && instr->def.bit_size == 32) {
Temp mask = bld.copy(bld.def(s1), Operand::c32(0x7fffffff));
if (ctx->block->fp_mode.denorm32 == fp_denorm_keep) {
bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), mask, src);
} else {
Temp tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), mask, src);
bld.sop2(aco_opcode::s_mul_f32, Definition(dst), Operand::c32(0x3f800000), tmp);
}
} else {
isel_err(&instr->instr, "Unimplemented NIR instr bit size");
}

4
src/amd/compiler/aco_instruction_selection_setup.cpp
View file

@ -330,8 +330,6 @@ init_context(isel_context* ctx, nir_shader* shader)
case nir_op_mov: break;
case nir_op_fmulz:
case nir_op_ffmaz:
case nir_op_fneg:
case nir_op_fabs:
case nir_op_f2f64:
case nir_op_u2f64:
case nir_op_i2f64:
@ -369,6 +367,8 @@ init_context(isel_context* ctx, nir_shader* shader)
case nir_op_fmax:
case nir_op_fmin:
case nir_op_fsat:
case nir_op_fneg:
case nir_op_fabs:
case nir_op_fsign:
case nir_op_i2f16:
case nir_op_i2f32: