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brw: Repack brw_inst fields

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In Release build, goes from 72 to 64 bytes, and now fits
in a single cacheline.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36730>
This commit is contained in:
Caio Oliveira 2025-08-22 00:27:16 -07:00 • committed by Marge Bot
parent 8ded571ef4
commit 2506540566
2 changed files with 10 additions and 9 deletions
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2
src/intel/compiler/brw_eu_defines.h
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@ -154,7 +154,7 @@ enum ENUM_PACKED brw_align1_3src_dst_horizontal_stride {
#define BRW_WE_ALL 1
/** @} */
enum opcode {
enum ENUM_PACKED opcode {
/* These are the actual hardware instructions. */
BRW_OPCODE_ILLEGAL,
BRW_OPCODE_SYNC,

17
src/intel/compiler/brw_inst.h
View file

@ -157,7 +157,8 @@ struct brw_inst : brw_exec_node {
*/
bool uses_address_register_implicitly() const;
uint8_t sources; /**< Number of brw_reg sources. */
enum opcode opcode;
brw_inst_kind kind;
/**
* Execution size of the instruction. This is used by the generator to
@ -175,14 +176,12 @@ struct brw_inst : brw_exec_node {
*/
uint8_t group;
uint16_t size_written; /**< Data written to the destination register in bytes. */
uint8_t sources; /**< Number of brw_reg sources. */
enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
enum brw_predicate predicate;
brw_inst_kind kind;
enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
tgl_swsb sched; /**< Scheduling info. */
uint16_t size_written; /**< Data written to the destination register in bytes. */
union {
struct {
@ -219,6 +218,10 @@ struct brw_inst : brw_exec_node {
uint16_t bits;
};
tgl_swsb sched; /**< Scheduling info. */
bblock_t *block;
brw_reg dst;
brw_reg *src;
@ -229,8 +232,6 @@ struct brw_inst : brw_exec_node {
const char *annotation;
/** @} */
#endif
bblock_t *block;
};
struct brw_send_inst : brw_inst {