radeonsi: align vertex buffer descriptor list size for optimal prefetch

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

src/gallium/drivers/radeonsi/si_cp_dma.c

@@ -434,7 +434,7 @@ static void cik_emit_prefetch_L2(struct si_context *sctx, struct r600_atom *atom
 	if (sctx->vertex_buffer_pointer_dirty) {
 		cik_prefetch_TC_L2_async(sctx, &sctx->vertex_buffers.buffer->b.b,
 					 sctx->vertex_buffers.buffer_offset,
-					 sctx->vertex_elements->count * 16);
+					 sctx->vertex_elements->desc_list_byte_size);
 	}
 	if (si_pm4_state_changed(sctx, ps))
 		cik_prefetch_shader_async(sctx, sctx->queued.named.ps);

src/gallium/drivers/radeonsi/si_descriptors.c

@@ -961,7 +961,8 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
 	 * directly through a staging buffer and don't go through
 	 * the fine-grained upload path.
 	 */
-	u_upload_alloc(sctx->b.uploader, 0, count * 16, 256, &desc->buffer_offset,
+	u_upload_alloc(sctx->b.uploader, 0, velems->desc_list_byte_size, 256,
+		       &desc->buffer_offset,
 		       (struct pipe_resource**)&desc->buffer, (void**)&ptr);
 	if (!desc->buffer)
 		return false;

src/gallium/drivers/radeonsi/si_state.c

@@ -3351,6 +3351,8 @@ static void *si_create_vertex_elements(struct pipe_context *ctx,
 		return NULL;
 
 	v->count = count;
+	v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
+
 	for (i = 0; i < count; ++i) {
 		const struct util_format_description *desc;
 		const struct util_format_channel_description *channel;

src/gallium/drivers/radeonsi/si_state.h

@@ -100,6 +100,8 @@ struct si_vertex_element
 {
 	unsigned			count;
 	unsigned			first_vb_use_mask;
+	/* Vertex buffer descriptor list size aligned for optimal prefetch. */
+	unsigned			desc_list_byte_size;
 
 	/* Two bits per attribute indicating the size of each vector component
 	 * in bytes if the size 3-workaround must be applied.