diff --git a/src/intel/compiler/brw/brw_opt_cmod_propagation.cpp b/src/intel/compiler/brw/brw_opt_cmod_propagation.cpp
index 310b56c8021..6a5e25bce6a 100644
--- a/src/intel/compiler/brw/brw_opt_cmod_propagation.cpp
+++ b/src/intel/compiler/brw/brw_opt_cmod_propagation.cpp
@@ -244,8 +244,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
            inst->opcode != BRW_OPCODE_MOV) ||
           inst->predicate != BRW_PREDICATE_NONE ||
           !inst->dst.is_null() ||
-          (inst->src[0].file != VGRF && inst->src[0].file != ATTR &&
-           inst->src[0].file != UNIFORM))
+          !inst->src[0].is_grf())
          continue;
 
       /* An ABS source modifier can only be handled when processing a compare
@@ -295,7 +294,10 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
 
             if (scan_inst->predicate ||
                 !scan_inst->dst.is_contiguous() ||
-                scan_inst->dst.offset != inst->src[0].offset ||
+                (scan_inst->dst.file != FIXED_GRF &&
+                 scan_inst->dst.offset != inst->src[0].offset) ||
+                (scan_inst->dst.file == FIXED_GRF &&
+                 scan_inst->dst.subnr != inst->src[0].subnr) ||
                 scan_inst->exec_size != inst->exec_size ||
                 scan_inst->group != inst->group)
                break;
diff --git a/src/intel/compiler/brw/test_opt_cmod_propagation.cpp b/src/intel/compiler/brw/test_opt_cmod_propagation.cpp
index 57b724681ca..e280a3e0696 100644
--- a/src/intel/compiler/brw/test_opt_cmod_propagation.cpp
+++ b/src/intel/compiler/brw/test_opt_cmod_propagation.cpp
@@ -2609,3 +2609,32 @@ TEST_F(cmod_propagation_test, different_group)
 
    EXPECT_NO_PROGRESS(brw_opt_cmod_propagation, bld);
 }
+
+TEST_F(cmod_propagation_test, fixed_grf_partial_overlap)
+{
+   brw_builder bld = make_shader();
+
+   brw_reg src0 = brw_make_reg(FIXED_GRF, 92, 0, 0, 0, BRW_TYPE_D,
+                               BRW_VERTICAL_STRIDE_8,
+                               BRW_WIDTH_4,
+                               BRW_HORIZONTAL_STRIDE_2,
+                               BRW_SWIZZLE_XYZW,
+                               WRITEMASK_XYZW);
+   brw_reg src1 = brw_make_reg(FIXED_GRF, 92, 4, 0, 0, BRW_TYPE_D,
+                               BRW_VERTICAL_STRIDE_8,
+                               BRW_WIDTH_4,
+                               BRW_HORIZONTAL_STRIDE_2,
+                               BRW_SWIZZLE_XYZW,
+                               WRITEMASK_XYZW);
+   brw_reg dst = brw_make_reg(FIXED_GRF, 94, 0, 0, 0, BRW_TYPE_D,
+                              BRW_VERTICAL_STRIDE_8,
+                              BRW_WIDTH_8,
+                              BRW_HORIZONTAL_STRIDE_1,
+                              BRW_SWIZZLE_XYZW,
+                              WRITEMASK_XYZW);
+
+   bld.CMP(dst, src0, brw_imm_d(0), BRW_CONDITIONAL_NZ);
+   bld.CMP(bld.null_reg_d(), src1, brw_imm_d(0), BRW_CONDITIONAL_L);
+
+   EXPECT_NO_PROGRESS(brw_opt_cmod_propagation, bld);
+}