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pan/bi: Use consistent wls naming

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Compare naming in the data structures.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8213>
This commit is contained in:
Alyssa Rosenzweig 2020-11-27 13:53:28 -05:00 • committed by Marge Bot
parent 3b6ef4ef10
commit 2470a6bc9a
2 changed files with 27 additions and 27 deletions
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52
src/panfrost/bifrost/ISA.xml
View file

@ -2324,7 +2324,7 @@
<mod name="seg" start="3" size="3">
<reserved/>
<reserved/>
<opt>wgl</opt>
<opt>wls</opt>
<reserved/>
<reserved/>
<reserved/>
@ -2339,7 +2339,7 @@
<mod name="seg" start="3" size="3">
<reserved/>
<reserved/>
<opt>wgl</opt>
<opt>wls</opt>
<reserved/>
<reserved/>
<reserved/>
@ -2457,25 +2457,25 @@
<ins name="+ACMPSTORE.i32" staging="r" mask="0xffdc0" exact="0x648c0">
<src start="0"/>
<src start="3"/>
<mod name="seg" start="9" size="1" opt="wgl"/>
<mod name="seg" start="9" size="1" opt="wls"/>
</ins>
<ins name="+ACMPSTORE.i64" staging="r" mask="0xffdc0" exact="0x64900">
<src start="0"/>
<src start="3"/>
<mod name="seg" start="9" size="1" opt="wgl"/>
<mod name="seg" start="9" size="1" opt="wls"/>
</ins>
<ins name="+ACMPXCHG.i32" staging="rw" mask="0xffdc0" exact="0x644c0">
<src start="0"/>
<src start="3"/>
<mod name="seg" start="9" size="1" opt="wgl"/>
<mod name="seg" start="9" size="1" opt="wls"/>
</ins>
<ins name="+ACMPXCHG.i64" staging="rw" mask="0xffdc0" exact="0x64500">
<src start="0"/>
<src start="3"/>
<mod name="seg" start="9" size="1" opt="wgl"/>
<mod name="seg" start="9" size="1" opt="wls"/>
</ins>
<ins name="+ATEST" staging="w" mask="0xfff00" exact="0xc8f00">
@ -2498,13 +2498,13 @@
<ins name="+AXCHG.i32" staging="rw" mask="0xffdc0" exact="0x640c0">
<src start="0"/>
<src start="3"/>
<mod name="seg" start="9" size="1" opt="wgl"/>
<mod name="seg" start="9" size="1" opt="wls"/>
</ins>
<ins name="+AXCHG.i64" staging="rw" mask="0xffdc0" exact="0x64100">
<src start="0"/>
<src start="3"/>
<mod name="seg" start="9" size="1" opt="wgl"/>
<mod name="seg" start="9" size="1" opt="wls"/>
</ins>
<ins name="+BARRIER" mask="0xfffff" exact="0xd7874"/>
@ -7044,7 +7044,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<opt>ubo</opt>
<reserved/>
@ -7059,7 +7059,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<opt>ubo</opt>
<reserved/>
@ -7118,7 +7118,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<opt>ubo</opt>
<reserved/>
@ -7133,7 +7133,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<opt>ubo</opt>
<reserved/>
@ -7170,7 +7170,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<opt>ubo</opt>
<reserved/>
@ -7185,7 +7185,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<opt>ubo</opt>
<reserved/>
@ -7200,7 +7200,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<opt>ubo</opt>
<reserved/>
@ -7284,7 +7284,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<opt>ubo</opt>
<reserved/>
@ -7456,7 +7456,7 @@
<mod name="seg" start="3" size="3">
<reserved/>
<reserved/>
<opt>wgl</opt>
<opt>wls</opt>
<reserved/>
<reserved/>
<reserved/>
@ -7471,7 +7471,7 @@
<mod name="seg" start="3" size="3">
<reserved/>
<reserved/>
<opt>wgl</opt>
<opt>wls</opt>
<reserved/>
<reserved/>
<reserved/>
@ -7498,7 +7498,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<reserved/>
<reserved/>
@ -7513,7 +7513,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<reserved/>
<reserved/>
@ -7528,7 +7528,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<reserved/>
<reserved/>
@ -7543,7 +7543,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<reserved/>
<reserved/>
@ -7558,7 +7558,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<reserved/>
<reserved/>
@ -7573,7 +7573,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<reserved/>
<reserved/>
@ -7588,7 +7588,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<reserved/>
<reserved/>
@ -7603,7 +7603,7 @@
<mod name="seg" start="6" size="3">
<reserved/>
<opt>none</opt>
<opt>wgl</opt>
<opt>wls</opt>
<opt>stream</opt>
<reserved/>
<reserved/>

2
src/panfrost/bifrost/gen_pack.py
View file

@ -203,7 +203,7 @@ def pack_seg(mod, opts, body, pack_exprs):
if len(opts) == 8:
body.append('assert(ins->segment);')
return 'ins->segment'
elif opts == ['none', 'wgl']:
elif opts == ['none', 'wls']:
body.append('assert(ins->segment == BI_SEGMENT_NONE || ins->segment == BI_SEGMENT_WLS);')
return 'ins->segment == BI_SEGMENT_WLS ? 1 : 0'
else: