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ac: move ring_offsets to ac_shader_args

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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19202>
This commit is contained in:
Rhys Perry 2022-10-20 13:16:18 +01:00 • committed by Marge Bot
parent 10a5035c83
commit 24618721d3
5 changed files with 11 additions and 8 deletions
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5
src/amd/common/ac_shader_args.h
View file

@ -75,6 +75,11 @@ struct ac_shader_args {
uint16_t num_sgprs_returned;
uint16_t num_vgprs_returned;
/* User data 0/1. GFX: descriptor list, Compute: scratch BO. These are the SGPRs used by RADV for
* scratch and have to be accessed using llvm.amdgcn.implicit.buffer.ptr for LLVM in that case.
*/
struct ac_arg ring_offsets;
/* VS */
struct ac_arg base_vertex;
struct ac_arg start_instance;

2
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -11319,7 +11319,7 @@ add_startpgm(struct isel_context* ctx)
/* Stash these in the program so that they can be accessed later when
* handling spilling.
*/
ctx->program->private_segment_buffer = get_arg(ctx, ctx->args->ring_offsets);
ctx->program->private_segment_buffer = get_arg(ctx, ctx->args->ac.ring_offsets);
if (ctx->program->gfx_level <= GFX10_3) {
ctx->program->scratch_offset = get_arg(ctx, ctx->args->ac.scratch_offset);

4
src/amd/vulkan/radv_nir_lower_abi.c
View file

@ -45,7 +45,7 @@ load_ring(nir_builder *b, unsigned ring, lower_abi_state *s)
struct ac_arg arg =
b->shader->info.stage == MESA_SHADER_TASK ?
s->args->task_ring_offsets :
s->args->ring_offsets;
s->args->ac.ring_offsets;
nir_ssa_def *ring_offsets = ac_nir_load_arg(b, &s->args->ac, arg);
ring_offsets = nir_pack_64_2x32_split(b, nir_channel(b, ring_offsets, 0), nir_channel(b, ring_offsets, 1));
@ -361,7 +361,7 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
case nir_intrinsic_load_sample_positions_amd: {
uint32_t sample_pos_offset = (RING_PS_SAMPLE_POSITIONS * 16) - 8;
nir_ssa_def *ring_offsets = ac_nir_load_arg(b, &s->args->ac, s->args->ring_offsets);
nir_ssa_def *ring_offsets = ac_nir_load_arg(b, &s->args->ac, s->args->ac.ring_offsets);
nir_ssa_def *addr = nir_pack_64_2x32(b, ring_offsets);
nir_ssa_def *sample_id = nir_umin(b, intrin->src[0].ssa, nir_imm_int(b, 7));
nir_ssa_def *offset = nir_ishl_imm(b, sample_id, 3); /* 2 floats containing samplepos.xy */

4
src/amd/vulkan/radv_shader_args.c
View file

@ -584,7 +584,7 @@ radv_declare_shader_args(enum amd_gfx_level gfx_level, const struct radv_pipelin
needs_view_index, has_ngg_query, has_ngg_provoking_vtx, key, &user_sgpr_info);
if (args->explicit_scratch_args) {
ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_DESC_PTR, &args->ring_offsets);
ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_DESC_PTR, &args->ac.ring_offsets);
}
if (stage == MESA_SHADER_TASK) {
ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_DESC_PTR, &args->task_ring_offsets);
@ -972,7 +972,7 @@ void
radv_declare_ps_epilog_args(enum amd_gfx_level gfx_level, const struct radv_ps_epilog_key *key,
struct radv_shader_args *args)
{
ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_DESC_PTR, &args->ring_offsets);
ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_DESC_PTR, &args->ac.ring_offsets);
if (gfx_level < GFX11)
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset);

4
src/amd/vulkan/radv_shader_args.h
View file

@ -36,9 +36,7 @@ struct radv_shader_args {
struct ac_shader_args ac;
struct ac_arg descriptor_sets[MAX_SETS];
/* User data 0/1. GFX: descriptor list, Compute: scratch BO */
struct ac_arg ring_offsets;
/* User data 2/3. same as the descriptor list above but for task shaders. */
/* User data 2/3. same as ring_offsets but for task shaders. */
struct ac_arg task_ring_offsets;
/* Streamout */