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aco: implement strict_wqm_coord_amd

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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22636>
This commit is contained in:
Rhys Perry 2023-04-14 15:44:43 +01:00 • committed by Marge Bot
parent 35c133a77b
commit 2447156b3c
2 changed files with 34 additions and 0 deletions
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27
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -9044,6 +9044,33 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
ctx->block->kind |= block_kind_export_end;
break;
}
case nir_intrinsic_strict_wqm_coord_amd: {
Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
Temp tmp = bld.tmp(RegClass::get(RegType::vgpr, dst.bytes()));
unsigned begin_size = nir_intrinsic_base(instr);
unsigned num_src = 1;
auto it = ctx->allocated_vec.find(src.id());
if (it != ctx->allocated_vec.end())
num_src = src.bytes() / it->second[0].bytes();
aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(
aco_opcode::p_create_vector, Format::PSEUDO, num_src + !!begin_size, 1)};
if (begin_size)
vec->operands[0] = Operand(RegClass::get(RegType::vgpr, begin_size));
for (unsigned i = 0; i < num_src; i++) {
Temp comp = it != ctx->allocated_vec.end() ? it->second[i] : src;
vec->operands[i + !!begin_size] = Operand(comp);
}
vec->definitions[0] = Definition(tmp);
ctx->block->instructions.emplace_back(std::move(vec));
bld.pseudo(aco_opcode::p_start_linear_vgpr, Definition(dst), tmp);
break;
}
default:
isel_err(&instr->instr, "Unimplemented intrinsic instr");
abort();

7
src/amd/compiler/aco_instruction_selection_setup.cpp
View file

@ -464,6 +464,13 @@ init_context(isel_context* ctx, nir_shader* shader)
nir_intrinsic_instr* intrinsic = nir_instr_as_intrinsic(instr);
if (!nir_intrinsic_infos[intrinsic->intrinsic].has_dest)
break;
if (intrinsic->intrinsic == nir_intrinsic_strict_wqm_coord_amd) {
regclasses[intrinsic->dest.ssa.index] =
RegClass::get(RegType::vgpr, intrinsic->dest.ssa.num_components * 4 +
nir_intrinsic_base(intrinsic))
.as_linear();
break;
}
RegType type = RegType::sgpr;
switch (intrinsic->intrinsic) {
case nir_intrinsic_load_push_constant: