fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-20 11:40:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

anv/iris: implement Wa_18040903259
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
Details
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details

Browse source 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34433>
This commit is contained in:
Lionel Landwerlin 2025-04-09 17:54:33 +03:00 • committed by Marge Bot
parent d123aedfc7
commit 243c01c703
2 changed files with 54 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

35
src/gallium/drivers/iris/iris_state.c
View file

@ -10121,16 +10121,41 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
flags |= PIPE_CONTROL_DEPTH_STALL;
}
#if INTEL_WA_1607156449_GFX_VER
#if INTEL_WA_1607156449_GFX_VER || INTEL_NEEDS_WA_18040903259
/* Wa_1607156449: For COMPUTE Workload - Any PIPE_CONTROL command with
* POST_SYNC Operation Enabled MUST be preceded by a PIPE_CONTROL with
* CS_STALL Bit set (with No POST_SYNC ENABLED)
*
* Wa_18040903259 says that timestamp are incorrect (not doing the CS Stall
* prior to writing the timestamp) with a command like this:
*
* PIPE_CONTROL(CS Stall, Post Sync = Timestamp)
*
* should be turned into :
*
* PIPE_CONTROL(CS Stall)
* PIPE_CONTROL(CS Stall, Post Sync = Timestamp)
*
* Also : "This WA needs to be applied only when we have done a Compute
* Walker and there is a request for a Timestamp."
*
* At the moment it's unclear whether all other parameters should go in the
* first or second PIPE_CONTROL. It seems logical that it should go to the
* first so that the timestamp accounts for all the associated flushes.
*/
if (intel_needs_workaround(devinfo, 1607156449) &&
if ((intel_needs_workaround(devinfo, 1607156449) ||
intel_needs_workaround(devinfo, 18040903259)) &&
IS_COMPUTE_PIPELINE(batch) &&
flags_to_post_sync_op(flags) != NoWrite) {
iris_emit_raw_pipe_control(batch, "Wa_1607156449",
PIPE_CONTROL_CS_STALL, NULL, 0, 0);
(flags & (PIPE_CONTROL_WRITE_TIMESTAMP |
PIPE_CONTROL_WRITE_IMMEDIATE))) {
iris_emit_raw_pipe_control(batch,
"workaround: Wa_1607156449/Wa_18040903259",
(flags & ~(PIPE_CONTROL_WRITE_TIMESTAMP |
PIPE_CONTROL_WRITE_IMMEDIATE)),
NULL, 0, 0);
flags &= (PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_WRITE_IMMEDIATE |
PIPE_CONTROL_WRITE_TIMESTAMP);
}
#endif

30
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -2450,18 +2450,36 @@ emit_pipe_control(struct anv_batch *batch,
/* XXX - insert all workarounds and GFX specific things below. */
#if INTEL_WA_1607156449_GFX_VER
#if INTEL_WA_1607156449_GFX_VER || INTEL_NEEDS_WA_18040903259
/* Wa_1607156449: For COMPUTE Workload - Any PIPE_CONTROL command with
* POST_SYNC Operation Enabled MUST be preceded by a PIPE_CONTROL with
* CS_STALL Bit set (with No POST_SYNC ENABLED)
*
* Wa_18040903259 says that timestamp are incorrect (not doing the CS Stall
* prior to writing the timestamp) with a command like this:
*
* PIPE_CONTROL(CS Stall, Post Sync = Timestamp)
*
* should be turned into :
*
* PIPE_CONTROL(CS Stall)
* PIPE_CONTROL(CS Stall, Post Sync = Timestamp)
*
* Also : "This WA needs to be applied only when we have done a Compute
* Walker and there is a request for a Timestamp."
*
* At the moment it's unclear whether all other parameters should go in the
* first or second PIPE_CONTROL. It seems logical that it should go to the
* first so that the timestamp accounts for all the associated flushes.
*/
if (intel_needs_workaround(devinfo, 1607156449) &&
if ((intel_needs_workaround(devinfo, 1607156449) ||
intel_needs_workaround(devinfo, 18040903259)) &&
current_pipeline == GPGPU &&
post_sync_op != NoWrite) {
anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) {
pipe.CommandStreamerStallEnable = true;
anv_debug_dump_pc(pipe, "Wa_14014966230");
};
emit_pipe_control(batch, devinfo, current_pipeline,
NoWrite, ANV_NULL_ADDRESS, 0,
bits, "Wa_18040903259/Wa_18040903259");
bits = ANV_PIPE_CS_STALL_BIT;
}
#endif