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i965: Always use the pre-computed offset for the relocation entry
We must be careful to only compute the address once based on the per-context information (rather than accessing the unlocked global bo->offset64) so that the value in the batch does match the reloc.presumed_offset we declare to the kernel. Otherwise, highly unlikely, but we may see GPU hangs in multithreaded users. The only real complication here is isl_surf_fill_state() which needs to adjust the reloc.delta to both general a tile offset and to encode state into the lower 12 bits. (Rebased on ISL changes by Ken.) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Chris Wilson
Kenneth Graunke
parent
1d0bd0d174
commit
2410deefff
2 changed files with 36 additions and 42 deletions
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@ -154,13 +154,13 @@ brw_emit_surface_state(struct brw_context *brw,
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case ISL_AUX_USAGE_CCS_E:
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aux_surf = &mt->mcs_buf->surf;
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aux_bo = mt->mcs_buf->bo;
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aux_offset = mt->mcs_buf->bo->offset64 + mt->mcs_buf->offset;
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aux_offset = mt->mcs_buf->offset;
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break;
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case ISL_AUX_USAGE_HIZ:
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aux_surf = &mt->hiz_buf->surf;
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aux_bo = mt->hiz_buf->bo;
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aux_offset = mt->hiz_buf->bo->offset64;
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aux_offset = 0;
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break;
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case ISL_AUX_USAGE_NONE:
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@ -180,28 +180,29 @@ brw_emit_surface_state(struct brw_context *brw,
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surf_offset);
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isl_surf_fill_state(&brw->isl_dev, state, .surf = &mt->surf, .view = &view,
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.address = mt->bo->offset64 + offset,
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.address = brw_emit_reloc(&brw->batch,
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*surf_offset + brw->isl_dev.ss.addr_offset,
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mt->bo, offset, read_domains, write_domains),
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.aux_surf = aux_surf, .aux_usage = aux_usage,
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.aux_address = aux_offset,
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.mocs = mocs, .clear_color = clear_color,
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.x_offset_sa = tile_x, .y_offset_sa = tile_y);
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brw_emit_reloc(&brw->batch, *surf_offset + brw->isl_dev.ss.addr_offset,
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mt->bo, offset, read_domains, write_domains);
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if (aux_surf) {
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/* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the
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* upper 20 bits of the GPU address of the MCS buffer; the lower 12 bits
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* contain other control information. Since buffer addresses are always
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* on 4k boundaries (and thus have their lower 12 bits zero), we can use
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* an ordinary reloc to do the necessary address translation.
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*
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* FIXME: move to the point of assignment.
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*/
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assert((aux_offset & 0xfff) == 0);
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uint32_t *aux_addr = state + brw->isl_dev.ss.aux_addr_offset;
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brw_emit_reloc(&brw->batch,
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*surf_offset + brw->isl_dev.ss.aux_addr_offset,
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aux_bo, *aux_addr - aux_bo->offset64,
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read_domains, write_domains);
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*aux_addr = brw_emit_reloc(&brw->batch,
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*surf_offset +
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brw->isl_dev.ss.aux_addr_offset,
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aux_bo, *aux_addr,
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read_domains, write_domains);
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}
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}
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@ -611,18 +612,16 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
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out_offset);
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isl_buffer_fill_state(&brw->isl_dev, dw,
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.address = (bo ? bo->offset64 : 0) + buffer_offset,
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.address = !bo ? buffer_offset :
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brw_emit_reloc(&brw->batch,
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*out_offset + brw->isl_dev.ss.addr_offset,
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bo, buffer_offset,
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I915_GEM_DOMAIN_SAMPLER,
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(rw ? I915_GEM_DOMAIN_SAMPLER : 0)),
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.size = buffer_size,
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.format = surface_format,
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.stride = pitch,
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.mocs = tex_mocs[brw->gen]);
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if (bo) {
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brw_emit_reloc(&brw->batch, *out_offset + brw->isl_dev.ss.addr_offset,
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bo, buffer_offset,
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I915_GEM_DOMAIN_SAMPLER,
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(rw ? I915_GEM_DOMAIN_SAMPLER : 0));
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}
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}
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void
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@ -785,17 +784,15 @@ brw_update_sol_surface(struct brw_context *brw,
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BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
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surface_format << BRW_SURFACE_FORMAT_SHIFT |
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BRW_SURFACE_RC_READ_WRITE;
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surf[1] = bo->offset64 + offset_bytes; /* reloc */
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surf[1] = brw_emit_reloc(&brw->batch,
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*out_offset + 4, bo, offset_bytes,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
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surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
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height << BRW_SURFACE_HEIGHT_SHIFT);
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surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
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pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
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surf[4] = 0;
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surf[5] = 0;
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/* Emit relocation to surface contents. */
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brw_emit_reloc(&brw->batch, *out_offset + 4, bo, offset_bytes,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
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}
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/* Creates a new WM constant buffer reflecting the current fragment program's
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@ -903,7 +900,9 @@ brw_emit_null_surface_state(struct brw_context *brw,
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1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
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1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
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}
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surf[1] = bo ? bo->offset64 : 0;
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surf[1] = !bo ? 0 :
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brw_emit_reloc(&brw->batch, *out_offset + 4, bo, 0,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
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surf[2] = ((width - 1) << BRW_SURFACE_WIDTH_SHIFT |
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(height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
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@ -916,11 +915,6 @@ brw_emit_null_surface_state(struct brw_context *brw,
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pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
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surf[4] = multisampling_state;
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surf[5] = 0;
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if (bo) {
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brw_emit_reloc(&brw->batch, *out_offset + 4, bo, 0,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
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}
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}
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/**
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@ -977,8 +971,12 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
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/* reloc */
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assert(mt->offset % mt->cpp == 0);
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surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
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mt->bo->offset64 + mt->offset);
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surf[1] = brw_emit_reloc(&brw->batch, offset + 4, mt->bo,
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mt->offset +
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intel_renderbuffer_get_tile_offsets(irb,
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&tile_x,
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&tile_y),
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
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surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
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(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
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@ -1021,9 +1019,6 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
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}
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}
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brw_emit_reloc(&brw->batch, offset + 4, mt->bo, surf[1] - mt->bo->offset64,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
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return offset;
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}
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@ -5053,14 +5053,13 @@ genX(update_sampler_state)(struct brw_context *brw,
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texObj->StencilSampling,
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&border_color_offset);
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}
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samp_st.BorderColorPointer = border_color_offset;
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if (GEN_GEN < 6) {
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samp_st.BorderColorPointer += brw->batch.bo->offset64; /* reloc */
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brw_emit_reloc(&brw->batch, batch_offset_for_sampler_state + 8,
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brw->batch.bo, border_color_offset,
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I915_GEM_DOMAIN_SAMPLER, 0);
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samp_st.BorderColorPointer =
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brw_emit_reloc(&brw->batch, batch_offset_for_sampler_state + 8,
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brw->batch.bo, border_color_offset,
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I915_GEM_DOMAIN_SAMPLER, 0);
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} else {
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samp_st.BorderColorPointer = border_color_offset;
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}
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#if GEN_GEN >= 8
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