From 23f7e06cd8d40569f8bfabde9c01d1597573abef Mon Sep 17 00:00:00 2001 From: Emma Anholt Date: Wed, 1 Sep 2021 17:06:13 -0700 Subject: [PATCH] freedreno/ir3: Don't use isam for coherent image loads on a6xx. If the coherent flag is present, then we need to not have an incoherent cache between us and previous stores to the image that were also decorated as coherent. isam apparently (unsurprisingly) goes through a texture cache. Use ldib instead, so that we don't get the wrong result. We need a similar fix for pre-a6xx, but we don't have emit_intrinsic_load_image for those (yet). Part-of: --- src/freedreno/ci/deqp-freedreno-a630-fails.txt | 6 ------ src/freedreno/ir3/ir3_compiler_nir.c | 8 ++++++++ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/freedreno/ci/deqp-freedreno-a630-fails.txt b/src/freedreno/ci/deqp-freedreno-a630-fails.txt index 8400b703228..d9748552cfa 100644 --- a/src/freedreno/ci/deqp-freedreno-a630-fails.txt +++ b/src/freedreno/ci/deqp-freedreno-a630-fails.txt @@ -20,17 +20,11 @@ KHR-GLES31.core.gpu_shader5.fma_precision_vec2,Fail KHR-GLES31.core.gpu_shader5.fma_precision_vec3,Fail KHR-GLES31.core.gpu_shader5.fma_precision_vec4,Fail -# "Got red: 1, expected 0.00392157, at (1, 0)" -KHR-GLES31.core.compute_shader.resource-image,Fail - # Lots of errors like "[279] Check failed. Received: [3,0,0,2] instead of: [5,0,0,2]" KHR-GLES31.core.geometry_shader.layered_framebuffer.depth_support,Fail KHR-GLES31.core.geometry_shader.layered_framebuffer.stencil_support,Fail -# " [31] Check failed. Received: [3,0,0,2] instead of: [5,0,0,2]" -KHR-GLES31.core.shader_image_load_store.basic-glsl-misc-fs,Fail - # " Pixel data comparison failed; expected: (0.1, 0.2, 0.3, 0.4) rendered: (0, 0, 0, 0) epsilon: 0.00392157 # Pixel data comparison failed at esextcTessellationShaderPoints.cpp:597" KHR-GLES31.core.tessellation_shader.tessellation_shader_point_mode.point_rendering,Fail diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index e3c10be1b4d..e6a1c0c289c 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -1209,6 +1209,14 @@ static void emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr, struct ir3_instruction **dst) { + /* Coherent accesses have to go directly to memory, rather than through + * ISAM's texture cache (which isn't coherent with image stores). + */ + if (nir_intrinsic_access(intr) & ACCESS_COHERENT && ctx->compiler->gen >= 6) { + ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst); + return; + } + struct ir3_block *b = ctx->block; struct tex_src_info info = get_image_samp_tex_src(ctx, intr); struct ir3_instruction *sam;