fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-04-05 19:00:35 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

anv: enable non uniform texture offset lowering

Browse source 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33138>
This commit is contained in:
Lionel Landwerlin 2025-01-21 15:55:34 +02:00 • committed by Marge Bot
parent 4346210ae6
commit 23de5abcb5
1 changed files with 31 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

32
src/intel/vulkan/anv_pipeline.c
View file

@ -936,6 +936,25 @@ accept_64bit_atomic_cb(const nir_intrinsic_instr *intrin, const void *data)
intrin->def.bit_size == 64;
}
static bool
lower_non_tg4_non_uniform_offsets(const nir_tex_instr *tex,
unsigned index, void *data)
{
/* HW cannot deal with divergent surfaces/samplers */
if (tex->src[index].src_type == nir_tex_src_texture_offset ||
tex->src[index].src_type == nir_tex_src_texture_handle ||
tex->src[index].src_type == nir_tex_src_sampler_offset ||
tex->src[index].src_type == nir_tex_src_sampler_handle)
return true;
if (tex->src[index].src_type == nir_tex_src_offset) {
/* HW can deal with TG4 divergent offsets only */
return tex->op != nir_texop_tg4;
}
return false;
}
static void
anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
void *mem_ctx,
@ -1059,7 +1078,17 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
enum nir_lower_non_uniform_access_type lower_non_uniform_access_types =
nir_lower_non_uniform_texture_access |
nir_lower_non_uniform_image_access |
nir_lower_non_uniform_get_ssbo_size;
nir_lower_non_uniform_get_ssbo_size |
nir_lower_non_uniform_texture_offset_access;
/* For textures, images, sampler, NonUniform decoration is required but not
* for offsets, so we rely on divergence information for this. Offsets used
* to be constants until KHR_maintenance8.
*/
if (pipeline->device->vk.enabled_features.maintenance8) {
nir_foreach_function_impl(impl, nir)
nir_metadata_require(impl, nir_metadata_divergence);
}
/* In practice, most shaders do not have non-uniform-qualified
* accesses (see
@ -1075,6 +1104,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
NIR_PASS(_, nir, nir_lower_non_uniform_access,
&(nir_lower_non_uniform_access_options) {
.types = lower_non_uniform_access_types,
.tex_src_callback = lower_non_tg4_non_uniform_offsets,
.callback = NULL,
});