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intel/nir/rt: add a new number of SIMD lanes per DSS helper

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v2: Add prefix brw_nir_rt (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
This commit is contained in:
Lionel Landwerlin 2021-06-21 13:56:32 +03:00 • committed by Marge Bot
parent 61c9b7a82e
commit 23ce94ff7e
1 changed files with 9 additions and 0 deletions
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9
src/intel/compiler/brw_nir_rt_builder.h
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@ -33,6 +33,15 @@ brw_load_btd_dss_id(nir_builder *b)
return nir_build_load_topology_id_intel(b, .base = BRW_TOPOLOGY_ID_DSS);
}
static inline nir_ssa_def *
brw_nir_rt_load_num_simd_lanes_per_dss(nir_builder *b,
const struct intel_device_info *devinfo)
{
return nir_imm_int(b, devinfo->num_thread_per_eu *
devinfo->max_eus_per_subslice *
16 /* The RT computation is based off SIMD16 */);
}
/* We have our own load/store scratch helpers because they emit a global
* memory read or write based on the scratch_base_ptr system value rather
* than a load/store_scratch intrinsic.