From 23b1df795369d52798d2bcf454e667c19d033277 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 20 Dec 2024 15:12:39 +0100 Subject: [PATCH] radv: use VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA for meta pipelines Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/meta/radv_meta_blit.c | 8 +++---- src/amd/vulkan/meta/radv_meta_blit2d.c | 26 +++++++++------------- src/amd/vulkan/meta/radv_meta_clear.c | 11 ++++----- src/amd/vulkan/meta/radv_meta_decompress.c | 3 +-- src/amd/vulkan/meta/radv_meta_fast_clear.c | 5 +---- src/amd/vulkan/meta/radv_meta_resolve.c | 3 +-- src/amd/vulkan/meta/radv_meta_resolve_fs.c | 16 +++++-------- src/amd/vulkan/radv_pipeline_graphics.c | 7 ------ src/amd/vulkan/radv_pipeline_graphics.h | 1 - 9 files changed, 26 insertions(+), 54 deletions(-) diff --git a/src/amd/vulkan/meta/radv_meta_blit.c b/src/amd/vulkan/meta/radv_meta_blit.c index ffc84cb0b1e..81afa272238 100644 --- a/src/amd/vulkan/meta/radv_meta_blit.c +++ b/src/amd/vulkan/meta/radv_meta_blit.c @@ -670,7 +670,7 @@ create_pipeline(struct radv_device *device, VkImageAspectFlagBits aspect, enum g .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo){ .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO, - .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP, + .topology = VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA, .primitiveRestartEnable = false, }, .pViewportState = @@ -762,10 +762,8 @@ create_pipeline(struct radv_device *device, VkImageAspectFlagBits aspect, enum g unreachable("Unhandled aspect"); } - const struct radv_graphics_pipeline_create_info radv_pipeline_info = {.use_rectlist = true}; - - result = radv_graphics_pipeline_create(radv_device_to_handle(device), device->meta_state.cache, &vk_pipeline_info, - &radv_pipeline_info, &device->meta_state.alloc, pipeline); + result = radv_CreateGraphicsPipelines(radv_device_to_handle(device), device->meta_state.cache, 1, &vk_pipeline_info, + &device->meta_state.alloc, pipeline); ralloc_free(vs); ralloc_free(fs); return result; diff --git a/src/amd/vulkan/meta/radv_meta_blit2d.c b/src/amd/vulkan/meta/radv_meta_blit2d.c index 7cc6502ba3d..5fb6427faa3 100644 --- a/src/amd/vulkan/meta/radv_meta_blit2d.c +++ b/src/amd/vulkan/meta/radv_meta_blit2d.c @@ -573,7 +573,7 @@ create_color_pipeline(struct radv_device *device, enum blit2d_src_type src_type, .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo){ .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO, - .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP, + .topology = VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA, .primitiveRestartEnable = false, }, .pViewportState = @@ -626,10 +626,8 @@ create_color_pipeline(struct radv_device *device, enum blit2d_src_type src_type, .subpass = 0, }; - const struct radv_graphics_pipeline_create_info radv_pipeline_info = {.use_rectlist = true}; - - result = radv_graphics_pipeline_create(radv_device_to_handle(device), device->meta_state.cache, &vk_pipeline_info, - &radv_pipeline_info, &device->meta_state.alloc, pipeline); + result = radv_CreateGraphicsPipelines(radv_device_to_handle(device), device->meta_state.cache, 1, &vk_pipeline_info, + &device->meta_state.alloc, pipeline); ralloc_free(vs); ralloc_free(fs); @@ -724,7 +722,7 @@ create_depth_only_pipeline(struct radv_device *device, enum blit2d_src_type src_ .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo){ .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO, - .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP, + .topology = VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA, .primitiveRestartEnable = false, }, .pViewportState = @@ -802,10 +800,8 @@ create_depth_only_pipeline(struct radv_device *device, enum blit2d_src_type src_ .subpass = 0, }; - const struct radv_graphics_pipeline_create_info radv_pipeline_info = {.use_rectlist = true}; - - result = radv_graphics_pipeline_create(radv_device_to_handle(device), device->meta_state.cache, &vk_pipeline_info, - &radv_pipeline_info, &device->meta_state.alloc, pipeline); + result = radv_CreateGraphicsPipelines(radv_device_to_handle(device), device->meta_state.cache, 1, &vk_pipeline_info, + &device->meta_state.alloc, pipeline); ralloc_free(vs); ralloc_free(fs); @@ -900,7 +896,7 @@ create_stencil_only_pipeline(struct radv_device *device, enum blit2d_src_type sr .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo){ .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO, - .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP, + .topology = VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA, .primitiveRestartEnable = false, }, .pViewportState = @@ -973,11 +969,9 @@ create_stencil_only_pipeline(struct radv_device *device, enum blit2d_src_type sr .subpass = 0, }; - const struct radv_graphics_pipeline_create_info radv_pipeline_info = {.use_rectlist = true}; - - result = radv_graphics_pipeline_create(radv_device_to_handle(device), device->meta_state.cache, &vk_pipeline_info, - &radv_pipeline_info, &device->meta_state.alloc, - &device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type]); + result = radv_CreateGraphicsPipelines(radv_device_to_handle(device), device->meta_state.cache, 1, &vk_pipeline_info, + &device->meta_state.alloc, + &device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type]); ralloc_free(vs); ralloc_free(fs); diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c index 6ad54417b0c..2cf5799544a 100644 --- a/src/amd/vulkan/meta/radv_meta_clear.c +++ b/src/amd/vulkan/meta/radv_meta_clear.c @@ -91,7 +91,7 @@ create_pipeline(struct radv_device *device, uint32_t samples, struct nir_shader .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo){ .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO, - .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP, + .topology = VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA, .primitiveRestartEnable = false, }, .pViewportState = @@ -209,9 +209,8 @@ create_color_pipeline(struct radv_device *device, uint32_t samples, uint32_t fra .pColorAttachmentFormats = att_formats, }; - struct radv_graphics_pipeline_create_info extra = { - .use_rectlist = true, - }; + struct radv_graphics_pipeline_create_info extra = {0}; + result = create_pipeline(device, samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state, &rendering_create_info, device->meta_state.clear_color_p_layout, &extra, &device->meta_state.alloc, pipeline); @@ -482,9 +481,7 @@ create_depthstencil_pipeline(struct radv_device *device, VkImageAspectFlags aspe .stencilAttachmentFormat = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) ? VK_FORMAT_S8_UINT : VK_FORMAT_UNDEFINED, }; - struct radv_graphics_pipeline_create_info extra = { - .use_rectlist = true, - }; + struct radv_graphics_pipeline_create_info extra = {0}; if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) { extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true; diff --git a/src/amd/vulkan/meta/radv_meta_decompress.c b/src/amd/vulkan/meta/radv_meta_decompress.c index 87f8ac2f326..02b1a337670 100644 --- a/src/amd/vulkan/meta/radv_meta_decompress.c +++ b/src/amd/vulkan/meta/radv_meta_decompress.c @@ -144,7 +144,7 @@ create_pipeline_gfx(struct radv_device *device, uint32_t samples, VkPipelineLayo .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo){ .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO, - .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP, + .topology = VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA, .primitiveRestartEnable = false, }, .pViewportState = @@ -204,7 +204,6 @@ create_pipeline_gfx(struct radv_device *device, uint32_t samples, VkPipelineLayo }; struct radv_graphics_pipeline_create_info extra = { - .use_rectlist = true, .depth_compress_disable = true, .stencil_compress_disable = true, }; diff --git a/src/amd/vulkan/meta/radv_meta_fast_clear.c b/src/amd/vulkan/meta/radv_meta_fast_clear.c index d53df9c871b..19212c2ec69 100644 --- a/src/amd/vulkan/meta/radv_meta_fast_clear.c +++ b/src/amd/vulkan/meta/radv_meta_fast_clear.c @@ -145,7 +145,7 @@ create_pipeline(struct radv_device *device, VkShaderModule vs_module_h, VkPipeli const VkPipelineInputAssemblyStateCreateInfo ia_state = { .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO, - .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP, + .topology = VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA, .primitiveRestartEnable = false, }; @@ -217,7 +217,6 @@ create_pipeline(struct radv_device *device, VkShaderModule vs_module_h, VkPipeli .subpass = 0, }, &(struct radv_graphics_pipeline_create_info){ - .use_rectlist = true, .custom_blend_mode = V_028808_CB_ELIMINATE_FAST_CLEAR, }, &device->meta_state.alloc, @@ -267,7 +266,6 @@ create_pipeline(struct radv_device *device, VkShaderModule vs_module_h, VkPipeli .subpass = 0, }, &(struct radv_graphics_pipeline_create_info){ - .use_rectlist = true, .custom_blend_mode = V_028808_CB_FMASK_DECOMPRESS, }, &device->meta_state.alloc, @@ -318,7 +316,6 @@ create_pipeline(struct radv_device *device, VkShaderModule vs_module_h, VkPipeli .subpass = 0, }, &(struct radv_graphics_pipeline_create_info){ - .use_rectlist = true, .custom_blend_mode = pdev->info.gfx_level >= GFX11 ? V_028808_CB_DCC_DECOMPRESS_GFX11 : V_028808_CB_DCC_DECOMPRESS_GFX8, }, diff --git a/src/amd/vulkan/meta/radv_meta_resolve.c b/src/amd/vulkan/meta/radv_meta_resolve.c index 35bb9f6d6eb..fca6f359570 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve.c +++ b/src/amd/vulkan/meta/radv_meta_resolve.c @@ -80,7 +80,7 @@ create_pipeline(struct radv_device *device, VkFormat format, VkPipeline *pipelin .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo){ .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO, - .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP, + .topology = VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA, .primitiveRestartEnable = false, }, .pViewportState = @@ -138,7 +138,6 @@ create_pipeline(struct radv_device *device, VkFormat format, VkPipeline *pipelin .subpass = 0, }, &(struct radv_graphics_pipeline_create_info){ - .use_rectlist = true, .custom_blend_mode = V_028808_CB_RESOLVE, }, &device->meta_state.alloc, pipeline); diff --git a/src/amd/vulkan/meta/radv_meta_resolve_fs.c b/src/amd/vulkan/meta/radv_meta_resolve_fs.c index 86ba5ee4ce7..54d6dafc40f 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve_fs.c +++ b/src/amd/vulkan/meta/radv_meta_resolve_fs.c @@ -131,7 +131,7 @@ create_resolve_pipeline(struct radv_device *device, int samples_log2, VkFormat f .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo){ .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO, - .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP, + .topology = VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA, .primitiveRestartEnable = false, }, .pViewportState = @@ -183,10 +183,8 @@ create_resolve_pipeline(struct radv_device *device, int samples_log2, VkFormat f .subpass = 0, }; - const struct radv_graphics_pipeline_create_info radv_pipeline_info = {.use_rectlist = true}; - - result = radv_graphics_pipeline_create(radv_device_to_handle(device), device->meta_state.cache, &vk_pipeline_info, - &radv_pipeline_info, &device->meta_state.alloc, pipeline); + result = radv_CreateGraphicsPipelines(radv_device_to_handle(device), device->meta_state.cache, 1, &vk_pipeline_info, + &device->meta_state.alloc, pipeline); ralloc_free(vs); ralloc_free(fs); return result; @@ -382,7 +380,7 @@ create_depth_stencil_resolve_pipeline(struct radv_device *device, int samples_lo .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo){ .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO, - .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP, + .topology = VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA, .primitiveRestartEnable = false, }, .pViewportState = @@ -435,10 +433,8 @@ create_depth_stencil_resolve_pipeline(struct radv_device *device, int samples_lo .subpass = 0, }; - const struct radv_graphics_pipeline_create_info radv_pipeline_info = {.use_rectlist = true}; - - result = radv_graphics_pipeline_create(radv_device_to_handle(device), device->meta_state.cache, &vk_pipeline_info, - &radv_pipeline_info, &device->meta_state.alloc, pipeline); + result = radv_CreateGraphicsPipelines(radv_device_to_handle(device), device->meta_state.cache, 1, &vk_pipeline_info, + &device->meta_state.alloc, pipeline); ralloc_free(vs); ralloc_free(fs); diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index ba29d88ffd0..9e89664ccfc 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -3281,13 +3281,6 @@ radv_pipeline_init_extra(struct radv_graphics_pipeline *pipeline, { pipeline->custom_blend_mode = extra->custom_blend_mode; - if (extra->use_rectlist) { - struct radv_dynamic_state *dynamic = &pipeline->dynamic_state; - dynamic->vk.ia.primitive_topology = V_008958_DI_PT_RECTLIST; - - pipeline->rast_prim = radv_conv_prim_to_gs_out(dynamic->vk.ia.primitive_topology, pipeline->is_ngg); - } - if (radv_pipeline_has_ds_attachments(state->rp)) { pipeline->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear); pipeline->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear); diff --git a/src/amd/vulkan/radv_pipeline_graphics.h b/src/amd/vulkan/radv_pipeline_graphics.h index c7219aed796..2cea168210f 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.h +++ b/src/amd/vulkan/radv_pipeline_graphics.h @@ -622,7 +622,6 @@ bool radv_needs_null_export_workaround(const struct radv_device *device, const s unsigned custom_blend_mode); struct radv_graphics_pipeline_create_info { - bool use_rectlist; bool db_depth_clear; bool db_stencil_clear; bool depth_compress_disable;