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From: Stephane Marchesin <marchesin@icps.u-strasbg.fr>

Browse source 
Attached is a patch that adds pci init code for mesa solo on radeon. It's been
tested on an itanium 2 with a radeon 7000 and it works here.
The patch adds a new field in the miniglx.conf config file, to choose between
pci and agp.
This commit is contained in:
Dave Airlie 2004-12-08 06:15:01 +00:00
parent e1b4fec71c
commit 23b033ad28
5 changed files with 105 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/glx/mini/driver.h
View file

@ -67,7 +67,8 @@ typedef struct DRIDriverContextRec {
int bpp;
int cpp;
int agpmode;
int isPCI;
unsigned long FBStart; /**< \brief physical address of the framebuffer */
unsigned long MMIOStart; /**< \brief physical address of the MMIO region */

3
src/glx/mini/example.miniglx.conf
View file

@ -14,6 +14,9 @@ clientDriverName=radeon_dri.so
# look in /proc/pci.
pciBusID=PCI:1:0:0
# Is the card PCI or AGP ?
isPCI=0
# Virtual screen dimensions. Can reduce this to save videocard memory
# at the expense of maximum window size available.
virtualWidth=1280

4
src/glx/mini/miniglx.c
View file

@ -830,6 +830,7 @@ static int __read_config_file( Display *dpy )
dpy->driverContext.cpp = 4;
dpy->rotateMode = 0;
dpy->driverContext.agpmode = 1;
dpy->driverContext.isPCI = 0;
fname = getenv("MINIGLX_CONF");
if (!fname) fname = "/etc/miniglx.conf";
@ -899,6 +900,9 @@ static int __read_config_file( Display *dpy )
if (sscanf(val, "%d", &dpy->driverContext.agpmode) != 1)
fprintf(stderr, "malformed agpmode: %s\n", opt);
}
else if (strcmp(opt, "isPCI") == 0) {
dpy->driverContext.isPCI = atoi(val) ? 1 : 0;
}
}
fclose(file);

2
src/mesa/drivers/dri/radeon/server/radeon.h
View file

@ -109,6 +109,8 @@ typedef struct {
drmSize registerSize; /**< \brief MMIO register map size */
drm_handle_t registerHandle; /**< \brief MMIO register map handle */
int IsPCI; /* Current card is a PCI card */
/**
* \name AGP
*/

101
src/mesa/drivers/dri/radeon/server/radeon_dri.c
View file

@ -421,6 +421,88 @@ static int RADEONDRIAgpInit( const DRIDriverContext *ctx, RADEONInfoPtr info)
return 1;
}
/* Initialize the PCI GART state. Request memory for use in PCI space,
* and initialize the Radeon registers to point to that memory.
*/
static int RADEONDRIPciInit(const DRIDriverContext *ctx, RADEONInfoPtr info)
{
int ret;
int flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL;
int s, l;
ret = drmScatterGatherAlloc(ctx->drmFD, info->gartSize*1024*1024,
&info->gartMemHandle);
if (ret < 0) {
fprintf(stderr, "[pci] Out of memory (%d)\n", ret);
return 0;
}
fprintf(stderr,
"[pci] %d kB allocated with handle 0x%08x\n",
info->gartSize*1024, info->gartMemHandle);
info->gartOffset = 0;
/* Initialize the CP ring buffer data */
info->ringStart = info->gartOffset;
info->ringMapSize = info->ringSize*1024*1024 + DRM_PAGE_SIZE;
info->ringReadOffset = info->ringStart + info->ringMapSize;
info->ringReadMapSize = DRM_PAGE_SIZE;
/* Reserve space for vertex/indirect buffers */
info->bufStart = info->ringReadOffset + info->ringReadMapSize;
info->bufMapSize = info->bufSize*1024*1024;
/* Reserve the rest for AGP textures */
info->gartTexStart = info->bufStart + info->bufMapSize;
s = (info->gartSize*1024*1024 - info->gartTexStart);
l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
info->gartTexMapSize = (s >> l) << l;
info->log2GARTTexGran = l;
if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) {
fprintf(stderr,
"[pci] Could not add ring mapping\n");
return 0;
}
fprintf(stderr,
"[pci] ring handle = 0x%08lx\n", info->ringHandle);
if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) {
fprintf(stderr,
"[pci] Could not add ring read ptr mapping\n");
return 0;
}
fprintf(stderr,
"[pci] ring read ptr handle = 0x%08lx\n",
info->ringReadPtrHandle);
if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) {
fprintf(stderr,
"[pci] Could not add vertex/indirect buffers mapping\n");
return 0;
}
fprintf(stderr,
"[pci] vertex/indirect buffers handle = 0x%08lx\n",
info->bufHandle);
if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize,
DRM_SCATTER_GATHER, 0, &info->gartTexHandle) < 0) {
fprintf(stderr,
"[pci] Could not add GART texture map mapping\n");
return 0;
}
fprintf(stderr,
"[pci] GART texture map handle = 0x%08lx\n",
info->gartTexHandle);
return 1;
}
/**
* \brief Initialize the kernel data structures and enable the CP engine.
@ -452,7 +534,7 @@ static int RADEONDRIKernelInit( const DRIDriverContext *ctx,
/* This is the struct passed to the kernel module for its initialization */
drmInfo.sarea_priv_offset = sizeof(drm_sarea_t);
drmInfo.is_pci = 0;
drmInfo.is_pci = ctx->isPCI;
drmInfo.cp_mode = RADEON_DEFAULT_CP_BM_MODE;
drmInfo.gart_size = info->gartSize*1024*1024;
drmInfo.ring_size = info->ringSize*1024*1024;
@ -526,7 +608,7 @@ static int RADEONDRIBufInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
info->bufNumBufs = drmAddBufs(ctx->drmFD,
info->bufMapSize / RADEON_BUFFER_SIZE,
RADEON_BUFFER_SIZE,
DRM_AGP_BUFFER,
ctx->isPCI ? DRM_SG_BUFFER : DRM_AGP_BUFFER,
info->bufStart);
if (info->bufNumBufs <= 0) {
@ -838,11 +920,16 @@ static int RADEONScreenInit( DRIDriverContext *ctx, RADEONInfoPtr info )
return 0;
}
/* Initialize AGP */
if (!RADEONDRIAgpInit(ctx, info)) {
return 0;
if (ctx->isPCI) {
/* Initialize PCI */
if (!RADEONDRIPciInit(ctx, info))
return 0;
}
else {
/* Initialize AGP */
if (!RADEONDRIAgpInit(ctx, info))
return 0;
}
/* Memory manager setup */
if (!RADEONMemoryInit(ctx, info)) {
@ -912,7 +999,7 @@ static int RADEONScreenInit( DRIDriverContext *ctx, RADEONInfoPtr info )
pRADEONDRI->height = ctx->shared.virtualHeight;
pRADEONDRI->depth = ctx->bpp; /* XXX: depth */
pRADEONDRI->bpp = ctx->bpp;
pRADEONDRI->IsPCI = 0;
pRADEONDRI->IsPCI = ctx->isPCI;
pRADEONDRI->AGPMode = ctx->agpmode;
pRADEONDRI->frontOffset = info->frontOffset;
pRADEONDRI->frontPitch = info->frontPitch;