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radeonsi/gfx9: use SET_UCONFIG_REG_INDEX packets when available

Browse source 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle 2018-06-29 00:08:26 +02:00
parent f18b2ac0db
commit 23af72af25
4 changed files with 18 additions and 5 deletions
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2
src/amd/common/ac_debug.c
View file

@ -233,6 +233,7 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
if (op == PKT3_SET_CONTEXT_REG ||
op == PKT3_SET_CONFIG_REG ||
op == PKT3_SET_UCONFIG_REG ||
op == PKT3_SET_UCONFIG_REG_INDEX ||
op == PKT3_SET_SH_REG)
fprintf(f, COLOR_CYAN "%s%s" COLOR_CYAN ":\n",
name, predicate);
@ -252,6 +253,7 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
ac_parse_set_reg_packet(f, count, SI_CONFIG_REG_OFFSET, ib);
break;
case PKT3_SET_UCONFIG_REG:
case PKT3_SET_UCONFIG_REG_INDEX:
ac_parse_set_reg_packet(f, count, CIK_UCONFIG_REG_OFFSET, ib);
break;
case PKT3_SET_SH_REG:

1
src/amd/common/sid.h
View file

@ -211,6 +211,7 @@
#define PKT3_SET_SH_REG 0x76
#define PKT3_SET_SH_REG_OFFSET 0x77
#define PKT3_SET_UCONFIG_REG 0x79 /* new for CIK */
#define PKT3_SET_UCONFIG_REG_INDEX 0x7A /* new for GFX9, CP ucode version >= 26 */
#define PKT3_LOAD_CONST_RAM 0x80
#define PKT3_WRITE_CONST_RAM 0x81
#define PKT3_DUMP_CONST_RAM 0x83

8
src/gallium/drivers/radeonsi/si_build_pm4.h
View file

@ -100,12 +100,18 @@ static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg
}
static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs,
struct si_screen *screen,
unsigned reg, unsigned idx,
unsigned value)
{
assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
assert(cs->current.cdw + 3 <= cs->current.max_dw);
radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0));
assert(idx != 0);
unsigned opcode = PKT3_SET_UCONFIG_REG_INDEX;
if (screen->info.chip_class < GFX9 ||
(screen->info.chip_class == GFX9 && screen->info.me_fw_version < 26))
opcode = PKT3_SET_UCONFIG_REG;
radeon_emit(cs, PKT3(opcode, 1, 0));
radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
radeon_emit(cs, value);
}

12
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -618,7 +618,9 @@ static void si_emit_draw_registers(struct si_context *sctx,
/* Draw state. */
if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
if (sctx->chip_class >= GFX9)
radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
radeon_set_uconfig_reg_idx(cs, sctx->screen,
R_030960_IA_MULTI_VGT_PARAM, 4,
ia_multi_vgt_param);
else if (sctx->chip_class >= CIK)
radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
else
@ -628,7 +630,8 @@ static void si_emit_draw_registers(struct si_context *sctx,
}
if (prim != sctx->last_prim) {
if (sctx->chip_class >= CIK)
radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
radeon_set_uconfig_reg_idx(cs, sctx->screen,
R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
else
radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
@ -716,8 +719,9 @@ static void si_emit_draw_packets(struct si_context *sctx,
}
if (sctx->chip_class >= GFX9) {
radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
2, index_type);
radeon_set_uconfig_reg_idx(cs, sctx->screen,
R_03090C_VGT_INDEX_TYPE, 2,
index_type);
} else {
radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
radeon_emit(cs, index_type);