From 238eeeacb243a2089ccbe6111fc4bfa01551cb13 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 7 Jun 2022 15:46:36 +0800 Subject: [PATCH] ac/llvm: get back intrinsics used by NGG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Will be used by radeonsi. Reviewed-by: Marek Olšák Signed-off-by: Qiang Yu Part-of: --- src/amd/llvm/ac_nir_to_llvm.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index ef753a066d8..7e394404359 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -4270,6 +4270,15 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins } break; } + case nir_intrinsic_load_packed_passthrough_primitive_amd: + result = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]); + break; + case nir_intrinsic_load_initial_edgeflags_amd: + if (ctx->stage == MESA_SHADER_VERTEX && !ctx->info->vs.blit_sgprs_amd) + result = ac_pack_edgeflags_for_export(&ctx->ac, ctx->args); + else + result = ctx->ac.i32_0; + break; case nir_intrinsic_has_input_vertex_amd: { LLVMValueRef num = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 0, 8); @@ -4282,6 +4291,12 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins result = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), num, ""); break; } + case nir_intrinsic_load_workgroup_num_input_vertices_amd: + result = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info), 12, 9); + break; + case nir_intrinsic_load_workgroup_num_input_primitives_amd: + result = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info), 22, 9); + break; case nir_intrinsic_alloc_vertices_and_primitives_amd: /* The caller should only call this conditionally for wave 0, so pass NULL to disable * the wave 0 check inside this function.