From 23590a4e98e41da90694ec10919082bf7e2c2166 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 5 Oct 2023 11:01:14 +0200 Subject: [PATCH] radv: Implement barriers for transfer queues. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The current flush flags in RADV don't really match the SDMA HW, so just always emit a NOP packet, for now. Signed-off-by: Timur Kristóf Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 48d525b8689..85697c80ebb 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -10489,7 +10489,17 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfo *dep_inf } radv_gang_barrier(cmd_buffer, 0, dst_stage_mask); - radv_cp_dma_wait_for_stages(cmd_buffer, src_stage_mask); + + if (cmd_buffer->qf == RADV_QUEUE_TRANSFER) { + /* SDMA NOP packet waits for all pending SDMA operations to complete. + * Note that GFX9+ is supposed to have RAW dependency tracking, but it's buggy + * so we can't rely on it fow now. + */ + radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 1); + radeon_emit(cmd_buffer->cs, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); + } else { + radv_cp_dma_wait_for_stages(cmd_buffer, src_stage_mask); + } cmd_buffer->state.flush_bits |= dst_flush_bits;