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radv: add missing cache flushes for DRLR feedback loops

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We should make sure the attachment is readable after the transition.

Fixes: 3af0f0129c ("radv: fix DRLR with subpass input attachments and feedback loops")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31200>
This commit is contained in:
Samuel Pitoiset 2024-09-17 09:56:25 +02:00 • committed by Marge Bot
parent ad3e6bb06a
commit 231688ad57
1 changed files with 13 additions and 0 deletions
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13
src/amd/vulkan/radv_cmd_buffer.c
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@ -9153,6 +9153,10 @@ radv_handle_color_fbfetch_output(struct radv_cmd_buffer *cmd_buffer, uint32_t in
att->layout = VK_IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT;
cmd_buffer->state.flush_bits |= radv_dst_access_flush(
cmd_buffer, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT,
VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT | VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT, att->iview->image);
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
}
@ -9187,6 +9191,11 @@ radv_handle_depth_fbfetch_output(struct radv_cmd_buffer *cmd_buffer)
.layerCount = att->iview->vk.layer_count,
};
/* Consider previous rendering work for WAW hazards. */
cmd_buffer->state.flush_bits |=
radv_src_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT,
VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, att->iview->image);
/* Force a transition to FEEDBACK_LOOP_OPTIMAL to decompress HTILE. */
radv_handle_image_transition(cmd_buffer, att->iview->image, att->layout,
VK_IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT, RADV_QUEUE_GENERAL,
@ -9194,6 +9203,10 @@ radv_handle_depth_fbfetch_output(struct radv_cmd_buffer *cmd_buffer)
att->layout = VK_IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT;
cmd_buffer->state.flush_bits |= radv_dst_access_flush(
cmd_buffer, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT,
VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT | VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT, att->iview->image);
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
}