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iris: fix register spilling on compute shaders on XeHP

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XeHP scratch space is handled differently. Commit ae18e1e707
implemented support for it, but handled it differently between render
and compute shaders: it calculates scratch_addr differently and
doesn't pin the buffer on compute. Make it work on compute shaders by
calling pin_scratch_space() from iris_compute_walker(), which fixes
both the address and the pinning.

This commit can be verified by the two-year-old-but-still-unreviewed
Piglit MR 234. You can also verify this by running a very simple
compute shader with INTEL_DEBUG=spill_fs.

References: https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/234
Fixes: ae18e1e707 ("iris: Add support for scratch on XeHP")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15070>
(cherry picked from commit d10fd5b7c9)
This commit is contained in:
Paulo Zanoni 2022-02-16 17:15:01 -08:00 • committed by Eric Engestrom
parent 2d12eb323e
commit 23094f01be
2 changed files with 4 additions and 5 deletions
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2
.pick_status.json
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@ -4936,7 +4936,7 @@
"description": "iris: fix register spilling on compute shaders on XeHP",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "ae18e1e707c4be005256305a30b747ab1bdf55d8"
},

7
src/gallium/drivers/iris/iris_state.c
View file

@ -6922,10 +6922,9 @@ iris_upload_compute_walker(struct iris_context *ice,
iris_emit_cmd(batch, GENX(CFE_STATE), cfe) {
cfe.MaximumNumberofThreads =
devinfo->max_cs_threads * devinfo->subslice_total - 1;
if (prog_data->total_scratch > 0) {
cfe.ScratchSpaceBuffer =
iris_get_scratch_surf(ice, prog_data->total_scratch)->offset >> 4;
}
uint32_t scratch_addr = pin_scratch_space(ice, batch, prog_data,
MESA_SHADER_COMPUTE);
cfe.ScratchSpaceBuffer = scratch_addr >> 4;
}
}