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synced 2026-05-08 06:58:05 +02:00
gallium: tgsi documentation updates and clarification for integer opcodes.
A lot of them were missing. Others were moved from the Compute ISA to a new Integer ISA section as that seemed more appropriate. Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
This commit is contained in:
Roland Scheidegger
parent
ae507b6260
commit
23025ed15d
1 changed files with 339 additions and 123 deletions
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@ -872,6 +872,16 @@ This instruction replicates its result.
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as an integer register.
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.. opcode:: CONT - Continue
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TBD
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.. note::
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Support for CONT is determined by a special capability bit,
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``TGSI_CONT_SUPPORTED``. See :ref:`Screen` for more information.
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.. opcode:: IF - Float If
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Start an IF ... ELSE .. ENDIF block. Condition evaluates to true if
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@ -977,6 +987,7 @@ These opcodes are primarily provided for special-use computational shaders.
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Support for these opcodes indicated by a special pipe capability bit (TBD).
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XXX so let's discuss it, yeah?
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XXX doesn't look like most of the opcodes really belong here.
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.. opcode:: CEIL - Ceiling
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@ -991,32 +1002,6 @@ XXX so let's discuss it, yeah?
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dst.w = \lceil src.w\rceil
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.. opcode:: I2F - Integer To Float
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.. math::
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dst.x = (float) src.x
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dst.y = (float) src.y
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dst.z = (float) src.z
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dst.w = (float) src.w
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.. opcode:: NOT - Bitwise Not
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.. math::
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dst.x = ~src.x
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dst.y = ~src.y
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dst.z = ~src.z
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dst.w = ~src.w
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.. opcode:: TRUNC - Truncate
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.. math::
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@ -1030,58 +1015,6 @@ XXX so let's discuss it, yeah?
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dst.w = trunc(src.w)
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.. opcode:: SHL - Shift Left
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.. math::
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dst.x = src0.x << src1.x
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dst.y = src0.y << src1.x
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dst.z = src0.z << src1.x
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dst.w = src0.w << src1.x
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.. opcode:: SHR - Shift Right
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.. math::
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dst.x = src0.x >> src1.x
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dst.y = src0.y >> src1.x
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dst.z = src0.z >> src1.x
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dst.w = src0.w >> src1.x
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.. opcode:: AND - Bitwise And
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.. math::
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dst.x = src0.x & src1.x
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dst.y = src0.y & src1.y
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dst.z = src0.z & src1.z
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dst.w = src0.w & src1.w
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.. opcode:: OR - Bitwise Or
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.. math::
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dst.x = src0.x | src1.x
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dst.y = src0.y | src1.y
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dst.z = src0.z | src1.z
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dst.w = src0.w | src1.w
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.. opcode:: MOD - Modulus
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.. math::
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@ -1095,51 +1028,12 @@ XXX so let's discuss it, yeah?
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dst.w = src0.w \bmod src1.w
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.. opcode:: XOR - Bitwise Xor
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.. math::
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dst.x = src0.x \oplus src1.x
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dst.y = src0.y \oplus src1.y
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dst.z = src0.z \oplus src1.z
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dst.w = src0.w \oplus src1.w
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.. opcode:: UCMP - Integer Conditional Move
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.. math::
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dst.x = src0.x ? src1.x : src2.x
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dst.y = src0.y ? src1.y : src2.y
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dst.z = src0.z ? src1.z : src2.z
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dst.w = src0.w ? src1.w : src2.w
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.. opcode:: UARL - Integer Address Register Load
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Moves the contents of the source register, assumed to be an integer, into the
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destination register, which is assumed to be an address (ADDR) register.
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.. opcode:: IABS - Integer Absolute Value
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.. math::
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dst.x = |src.x|
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dst.y = |src.y|
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dst.z = |src.z|
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dst.w = |src.w|
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.. opcode:: SAD - Sum Of Absolute Differences
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.. math::
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@ -1173,7 +1067,7 @@ XXX so let's discuss it, yeah?
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.. math::
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lod = src0
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lod = src0.x
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dst.x = texture_width(unit, lod)
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@ -1182,14 +1076,336 @@ XXX so let's discuss it, yeah?
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dst.z = texture_depth(unit, lod)
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.. opcode:: CONT - Continue
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Integer ISA
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^^^^^^^^^^^^^^^^^^^^^^^^
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These opcodes are used for integer operations.
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Support for these opcodes indicated by PIPE_SHADER_CAP_INTEGERS (all of them?)
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TBD
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.. note::
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.. opcode:: I2F - Signed Integer To Float
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Support for CONT is determined by a special capability bit,
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``TGSI_CONT_SUPPORTED``. See :ref:`Screen` for more information.
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Rounding is unspecified (round to nearest even suggested).
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.. math::
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dst.x = (float) src.x
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dst.y = (float) src.y
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dst.z = (float) src.z
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dst.w = (float) src.w
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.. opcode:: U2F - Unsigned Integer To Float
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Rounding is unspecified (round to nearest even suggested).
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.. math::
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dst.x = (float) src.x
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dst.y = (float) src.y
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dst.z = (float) src.z
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dst.w = (float) src.w
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.. opcode:: F2I - Float to Signed Integer
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Rounding is towards zero (truncate).
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Values outside signed range (including NaNs) produce undefined results.
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.. math::
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dst.x = (int) src.x
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dst.y = (int) src.y
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dst.z = (int) src.z
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dst.w = (int) src.w
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.. opcode:: F2U - Float to Unsigned Integer
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Rounding is towards zero (truncate).
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Values outside unsigned range (including NaNs) produce undefined results.
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.. math::
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dst.x = (unsigned) src.x
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dst.y = (unsigned) src.y
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dst.z = (unsigned) src.z
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dst.w = (unsigned) src.w
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.. opcode:: UADD - Integer Add
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This instruction works the same for signed and unsigned integers.
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The low 32bit of the result is returned.
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.. math::
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dst.x = src0.x + src1.x
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dst.y = src0.y + src1.y
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dst.z = src0.z + src1.z
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dst.w = src0.w + src1.w
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.. opcode:: UMAD - Integer Multiply And Add
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This instruction works the same for signed and unsigned integers.
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The multiplication returns the low 32bit (as does the result itself).
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.. math::
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dst.x = src0.x \times src1.x + src2.x
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dst.y = src0.y \times src1.y + src2.y
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dst.z = src0.z \times src1.z + src2.z
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dst.w = src0.w \times src1.w + src2.w
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.. opcode:: UMUL - Integer Multiply
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This instruction works the same for signed and unsigned integers.
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The low 32bit of the result is returned.
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.. math::
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dst.x = src0.x \times src1.x
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dst.y = src0.y \times src1.y
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dst.z = src0.z \times src1.z
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dst.w = src0.w \times src1.w
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.. opcode:: IDIV - Signed Integer Division
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TBD: behavior for division by zero.
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.. math::
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dst.x = src0.x \ src1.x
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dst.y = src0.y \ src1.y
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dst.z = src0.z \ src1.z
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dst.w = src0.w \ src1.w
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.. opcode:: UDIV - Unsigned Integer Division
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For division by zero, 0xffffffff is returned.
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.. math::
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dst.x = src0.x \ src1.x
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dst.y = src0.y \ src1.y
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dst.z = src0.z \ src1.z
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dst.w = src0.w \ src1.w
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.. opcode:: UMOD - Unsigned Integer Remainder
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If second arg is zero, 0xffffffff is returned.
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.. math::
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dst.x = src0.x \ src1.x
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dst.y = src0.y \ src1.y
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dst.z = src0.z \ src1.z
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dst.w = src0.w \ src1.w
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.. opcode:: NOT - Bitwise Not
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.. math::
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dst.x = ~src.x
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dst.y = ~src.y
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dst.z = ~src.z
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dst.w = ~src.w
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.. opcode:: AND - Bitwise And
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.. math::
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dst.x = src0.x & src1.x
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dst.y = src0.y & src1.y
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dst.z = src0.z & src1.z
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dst.w = src0.w & src1.w
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.. opcode:: OR - Bitwise Or
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.. math::
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dst.x = src0.x | src1.x
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dst.y = src0.y | src1.y
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dst.z = src0.z | src1.z
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dst.w = src0.w | src1.w
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.. opcode:: XOR - Bitwise Xor
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.. math::
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dst.x = src0.x \oplus src1.x
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dst.y = src0.y \oplus src1.y
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dst.z = src0.z \oplus src1.z
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dst.w = src0.w \oplus src1.w
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.. opcode:: IMAX - Maximum of Signed Integers
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.. math::
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dst.x = max(src0.x, src1.x)
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dst.y = max(src0.y, src1.y)
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dst.z = max(src0.z, src1.z)
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dst.w = max(src0.w, src1.w)
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.. opcode:: UMAX - Maximum of Unsigned Integers
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.. math::
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dst.x = max(src0.x, src1.x)
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dst.y = max(src0.y, src1.y)
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dst.z = max(src0.z, src1.z)
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dst.w = max(src0.w, src1.w)
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.. opcode:: IMIN - Minimum of Signed Integers
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.. math::
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dst.x = min(src0.x, src1.x)
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dst.y = min(src0.y, src1.y)
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dst.z = min(src0.z, src1.z)
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dst.w = min(src0.w, src1.w)
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.. opcode:: UMIN - Minimum of Unsigned Integers
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.. math::
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dst.x = min(src0.x, src1.x)
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dst.y = min(src0.y, src1.y)
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dst.z = min(src0.z, src1.z)
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dst.w = min(src0.w, src1.w)
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.. opcode:: SHL - Shift Left
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.. math::
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dst.x = src0.x << src1.x
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dst.y = src0.y << src1.x
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dst.z = src0.z << src1.x
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dst.w = src0.w << src1.x
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.. opcode:: ISHR - Arithmetic Shift Right (of Signed Integer)
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.. math::
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dst.x = src0.x >> src1.x
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dst.y = src0.y >> src1.x
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dst.z = src0.z >> src1.x
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dst.w = src0.w >> src1.x
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.. opcode:: USHR - Logical Shift Right
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.. math::
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dst.x = src0.x >> (unsigned) src1.x
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dst.y = src0.y >> (unsigned) src1.x
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dst.z = src0.z >> (unsigned) src1.x
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dst.w = src0.w >> (unsigned) src1.x
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.. opcode:: UCMP - Integer Conditional Move
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.. math::
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dst.x = src0.x ? src1.x : src2.x
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dst.y = src0.y ? src1.y : src2.y
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dst.z = src0.z ? src1.z : src2.z
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dst.w = src0.w ? src1.w : src2.w
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.. opcode:: IABS - Integer Absolute Value
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.. math::
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dst.x = |src.x|
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dst.y = |src.y|
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dst.z = |src.z|
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dst.w = |src.w|
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Geometry ISA
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Reference in a new issue