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pan/mdg: Fix temp count calculation
1. Always calculate when asked. This is the sort of optimization that just introduces bugs. Like one I hit when shuffling register indices around with the register access changes. 2. Ask before using in RA. 3. Account for precoloured blend inputs. Small shader-db hit, didn't investigate too much. total instructions in shared programs: 1518017 -> 1518168 (<.01%) instructions in affected programs: 2895 -> 3046 (5.22%) helped: 0 HURT: 24 Instructions are HURT. total bundles in shared programs: 646756 -> 646782 (<.01%) bundles in affected programs: 1119 -> 1145 (2.32%) helped: 1 HURT: 19 Bundles are HURT. total quadwords in shared programs: 1133694 -> 1133728 (<.01%) quadwords in affected programs: 1736 -> 1770 (1.96%) helped: 0 HURT: 20 Quadwords are HURT. total registers in shared programs: 90596 -> 90612 (0.02%) registers in affected programs: 108 -> 124 (14.81%) helped: 0 HURT: 16 Registers are HURT. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Cc: mesa-stable Reviewed-by: Italo Nicola <italonicola@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23769>
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2 changed files with 10 additions and 7 deletions
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@ -519,7 +519,7 @@ allocate_registers(compiler_context *ctx, bool *spilled)
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int work_count = max_work_registers(ctx);
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/* No register allocation to do with no SSA */
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mir_compute_temp_count(ctx);
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if (!ctx->temp_count)
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return NULL;
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@ -484,15 +484,18 @@ mir_flip(midgard_instruction *ins)
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void
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mir_compute_temp_count(compiler_context *ctx)
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{
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if (ctx->temp_count)
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return;
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unsigned max_dest = 0;
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unsigned max_index = 0;
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mir_foreach_instr_global(ctx, ins) {
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if (ins->dest < SSA_FIXED_MINIMUM)
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max_dest = MAX2(max_dest, ins->dest + 1);
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max_index = MAX2(max_index, ins->dest + 1);
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}
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ctx->temp_count = max_dest;
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if (ctx->blend_input != ~0)
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max_index = MAX2(max_index, ctx->blend_input + 1);
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if (ctx->blend_src1 != ~0)
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max_index = MAX2(max_index, ctx->blend_src1 + 1);
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ctx->temp_count = max_index;
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}
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