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radv: move SPI_PS_INPUT_ENA emission into radv_emit_ps_state

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The register values will depend on new fields in PS_STATE and it doesn't
seem like dynamic state belongs in radv_emit_fragment_shader_state.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41689>
This commit is contained in:
Marek Olšák 2026-05-17 21:30:30 -04:00 • committed by Marge Bot
parent caef0aebba
commit 22e40edfb9
1 changed files with 29 additions and 27 deletions
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56
src/amd/vulkan/radv_cmd_buffer.c
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@ -3626,7 +3626,6 @@ radv_emit_fragment_shader_state(struct radv_cmd_buffer *cmd_buffer, const struct
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
const uint32_t spi_ps_input_ena = ps ? ps->config.spi_ps_input_ena : 0;
const uint32_t spi_ps_input_addr = ps ? ps->config.spi_ps_input_addr : 0;
const uint32_t spi_ps_in_control = ps ? ps->regs.ps.spi_ps_in_control : 0;
struct radv_cmd_stream *cs = cmd_buffer->cs;
@ -3636,24 +3635,19 @@ radv_emit_fragment_shader_state(struct radv_cmd_buffer *cmd_buffer, const struct
const uint32_t pa_sc_hisz_control = ps ? ps->regs.ps.pa_sc_hisz_control : 0;
gfx12_begin_context_regs();
gfx12_opt_set_context_reg2(R_02865C_SPI_PS_INPUT_ENA, AC_TRACKED_SPI_PS_INPUT_ENA, spi_ps_input_ena,
spi_ps_input_addr);
gfx12_opt_set_context_reg(R_028660_SPI_PS_INPUT_ADDR, AC_TRACKED_SPI_PS_INPUT_ADDR, spi_ps_input_addr);
gfx12_opt_set_context_reg(R_028640_SPI_PS_IN_CONTROL, AC_TRACKED_SPI_PS_IN_CONTROL, spi_ps_in_control);
gfx12_opt_set_context_reg(R_028BBC_PA_SC_HISZ_CONTROL, AC_TRACKED_PA_SC_HISZ_CONTROL, pa_sc_hisz_control);
gfx12_end_context_regs();
} else if (pdev->info.has_set_context_pairs_packed) {
gfx11_begin_packed_context_regs();
gfx11_opt_set_context_reg2(R_0286CC_SPI_PS_INPUT_ENA, AC_TRACKED_SPI_PS_INPUT_ENA, spi_ps_input_ena,
spi_ps_input_addr);
gfx11_opt_set_context_reg(R_0286D0_SPI_PS_INPUT_ADDR, AC_TRACKED_SPI_PS_INPUT_ADDR, spi_ps_input_addr);
gfx11_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, AC_TRACKED_SPI_PS_IN_CONTROL, spi_ps_in_control);
gfx11_end_packed_context_regs();
} else {
const uint32_t pa_sc_shader_control = ps ? ps->regs.ps.pa_sc_shader_control : 0;
radeon_opt_set_context_reg2(R_0286CC_SPI_PS_INPUT_ENA, AC_TRACKED_SPI_PS_INPUT_ENA, spi_ps_input_ena,
spi_ps_input_addr);
radeon_opt_set_context_reg(R_0286D0_SPI_PS_INPUT_ADDR, AC_TRACKED_SPI_PS_INPUT_ADDR, spi_ps_input_addr);
if (pdev->info.gfx_level != GFX10_3) {
radeon_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, AC_TRACKED_SPI_PS_IN_CONTROL, spi_ps_in_control);
@ -8903,8 +8897,7 @@ radv_bind_fragment_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_
if (ps->info.ps.has_epilog)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PS_EPILOG_SHADER | RADV_CMD_DIRTY_PS_EPILOG_STATE;
if (radv_get_user_sgpr_info(ps, AC_UD_PS_STATE)->sgpr_idx != -1)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PS_STATE;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PS_STATE;
if (!previous_ps || previous_ps->info.ps.reads_fully_covered != ps->info.ps.reads_fully_covered)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_MSAA_STATE;
@ -11698,26 +11691,35 @@ radv_emit_ps_state(struct radv_cmd_buffer *cmd_buffer)
if (!ps)
return;
const uint32_t spi_ps_input_ena = ps->config.spi_ps_input_ena;
struct radv_cmd_stream *cs = cmd_buffer->cs;
radeon_begin(cs);
if (pdev->info.gfx_level >= GFX12)
radeon_opt_set_context_reg(R_02865C_SPI_PS_INPUT_ENA, AC_TRACKED_SPI_PS_INPUT_ENA, spi_ps_input_ena);
else
radeon_opt_set_context_reg(R_0286CC_SPI_PS_INPUT_ENA, AC_TRACKED_SPI_PS_INPUT_ENA, spi_ps_input_ena);
const uint32_t ps_state_offset = radv_get_user_sgpr_loc(ps, AC_UD_PS_STATE);
if (!ps_state_offset)
return;
const VkLineRasterizationModeEXT line_rast_mode = cmd_buffer->state.line_rast_mode;
const unsigned rasterization_samples = cmd_buffer->state.num_rast_samples;
const unsigned ps_iter_samples = radv_get_ps_iter_samples(cmd_buffer);
const uint16_t ps_iter_mask = ac_get_ps_iter_mask(ps_iter_samples);
const unsigned vgt_outprim_type = cmd_buffer->state.vgt_outprim_type;
const unsigned ps_state = SET_SGPR_FIELD(PS_STATE_NUM_SAMPLES, rasterization_samples) |
SET_SGPR_FIELD(PS_STATE_PS_ITER_MASK, ps_iter_mask) |
SET_SGPR_FIELD(PS_STATE_LINE_RAST_MODE, line_rast_mode) |
SET_SGPR_FIELD(PS_STATE_RAST_PRIM, vgt_outprim_type);
if (ps_state_offset) {
const VkLineRasterizationModeEXT line_rast_mode = cmd_buffer->state.line_rast_mode;
const unsigned rasterization_samples = cmd_buffer->state.num_rast_samples;
const unsigned ps_iter_samples = radv_get_ps_iter_samples(cmd_buffer);
const uint16_t ps_iter_mask = ac_get_ps_iter_mask(ps_iter_samples);
const unsigned vgt_outprim_type = cmd_buffer->state.vgt_outprim_type;
const unsigned ps_state = SET_SGPR_FIELD(PS_STATE_NUM_SAMPLES, rasterization_samples) |
SET_SGPR_FIELD(PS_STATE_PS_ITER_MASK, ps_iter_mask) |
SET_SGPR_FIELD(PS_STATE_LINE_RAST_MODE, line_rast_mode) |
SET_SGPR_FIELD(PS_STATE_RAST_PRIM, vgt_outprim_type);
radeon_begin(cmd_buffer->cs);
if (pdev->info.gfx_level >= GFX12) {
gfx12_push_sh_reg(ps_state_offset, ps_state);
} else {
radeon_set_sh_reg(ps_state_offset, ps_state);
if (pdev->info.gfx_level >= GFX12) {
gfx12_push_sh_reg(ps_state_offset, ps_state);
} else {
radeon_set_sh_reg(ps_state_offset, ps_state);
}
}
radeon_end();
}