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i965/hsw: Populate MOCS for STATE_BASE_ADDRESS (v2)

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Just spotted these unpopulated MOCS fields when comparing the code
against BSpec. Set the MOCS to the same as everywhere else in Haswell:
L3-cacheable.

v2: Annotate state packet fields (chadv).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
This commit is contained in:
Ville Syrjälä 2013-08-12 16:07:07 +03:00 • committed by Chad Versace
parent 10aa3677cc
commit 22161983c3
2 changed files with 11 additions and 3 deletions
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7
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -1038,13 +1038,16 @@ static void upload_state_base_address( struct brw_context *brw )
*/
if (brw->gen >= 6) {
uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
if (brw->gen == 6)
intel_emit_post_sync_nonzero_flush(brw);
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
/* General state base address: stateless DP read/write requests */
OUT_BATCH(1);
OUT_BATCH(mocs << 8 | /* General State Memory Object Control State */
mocs << 4 | /* Stateless Data Port Access Memory Object Control State */
1); /* General State Base Address Modify Enable */
/* Surface state base address:
* BINDING_TABLE_STATE
* SURFACE_STATE

7
src/mesa/drivers/dri/i965/gen6_blorp.cpp
View file

@ -74,9 +74,14 @@ void
gen6_blorp_emit_state_base_address(struct brw_context *brw,
const brw_blorp_params *params)
{
uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */
OUT_BATCH(mocs << 8 | /* GeneralStateMemoryObjectControlState */
mocs << 4 | /* StatelessDataPortAccessMemoryObjectControlState */
1); /* GeneralStateBaseAddressModifyEnable */
/* SurfaceStateBaseAddress */
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
/* DynamicStateBaseAddress */