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nvc0: mark buffer texture range valid for shader images

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Loosely based on radeonsi (Thanks to Nicolai).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 28590eb949)
This commit is contained in:
Samuel Pitoiset 2016-06-03 00:00:27 +02:00 • committed by Emil Velikov
parent 09f0e97d1c
commit 2185edf699
3 changed files with 31 additions and 0 deletions
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1
src/gallium/drivers/nouveau/nvc0/nvc0_context.h
View file

@ -333,6 +333,7 @@ void nve4_set_tex_handles(struct nvc0_context *);
void nvc0_validate_surfaces(struct nvc0_context *);
void nve4_set_surface_info(struct nouveau_pushbuf *, struct pipe_image_view *,
struct nvc0_context *);
void nvc0_mark_image_range_valid(const struct pipe_image_view *);
void nvc0_update_tic(struct nvc0_context *, struct nv50_tic_entry *,
struct nv04_resource *);

25
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
View file

@ -793,6 +793,23 @@ nvc0_get_surface_dims(struct pipe_image_view *view, int *width, int *height,
}
}
void
nvc0_mark_image_range_valid(const struct pipe_image_view *view)
{
struct nv04_resource *res = (struct nv04_resource *)view->resource;
const struct util_format_description *desc;
unsigned stride;
assert(view->resource->target == PIPE_BUFFER);
desc = util_format_description(view->format);
stride = desc->block.bits / 8;
util_range_add(&res->valid_buffer_range,
stride * (view->u.buf.first_element),
stride * (view->u.buf.last_element + 1));
}
void
nve4_set_surface_info(struct nouveau_pushbuf *push,
struct pipe_image_view *view,
@ -1011,6 +1028,9 @@ nvc0_validate_suf(struct nvc0_context *nvc0, int s)
address += view->u.buf.first_element * blocksize;
assert(!(address & 0xff));
if (view->access & PIPE_IMAGE_ACCESS_WRITE)
nvc0_mark_image_range_valid(view);
PUSH_DATAh(push, address);
PUSH_DATA (push, address);
PUSH_DATA (push, align(width * blocksize, 0x100));
@ -1106,6 +1126,11 @@ nve4_update_surface_bindings(struct nvc0_context *nvc0)
if (view->resource) {
struct nv04_resource *res = nv04_resource(view->resource);
if (res->base.target == PIPE_BUFFER) {
if (view->access & PIPE_IMAGE_ACCESS_WRITE)
nvc0_mark_image_range_valid(view);
}
nve4_set_surface_info(push, view, nvc0);
BCTX_REFN(nvc0->bufctx_3d, 3D_SUF, res, RDWR);
} else {

5
src/gallium/drivers/nouveau/nvc0/nve4_compute.c
View file

@ -214,6 +214,11 @@ nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
if (view->resource) {
struct nv04_resource *res = nv04_resource(view->resource);
if (res->base.target == PIPE_BUFFER) {
if (view->access & PIPE_IMAGE_ACCESS_WRITE)
nvc0_mark_image_range_valid(view);
}
nve4_set_surface_info(push, view, nvc0);
BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
} else {