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Revert "r600g: simplify states"

Browse source 
This reverts commit bd25e23bf3.

Apart from introducing a lot of hex magic numbers and being highly impenetable code,
it causes lots of lockups on an average piglit run that always runs without lockups.

Always run piglit before/after doing big things like this.
This commit is contained in:
Dave Airlie 2010-08-27 15:45:58 +10:00
parent a03d456f5a
commit 2184f3ec30
15 changed files with 1722 additions and 8279 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

61
src/gallium/drivers/r600/r600_blit.c
View file

@ -132,7 +132,7 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
unsigned srcx, unsigned srcy, unsigned srcz,
unsigned width, unsigned height)
{
util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
util_resource_copy_region(pipe, dst, subdst, dstx, dsty, dstz,
src, subsrc, srcx, srcy, srcz, width, height);
}
@ -190,7 +190,7 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
memcpy(bo->data, vbo, 128);
radeon_bo_unmap(rscreen->rw, bo);
rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 0);
rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 0);
if (rstate == NULL) {
radeon_bo_decref(rscreen->rw, bo);
return -ENOMEM;
@ -199,35 +199,33 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
/* set states (most default value are 0 and struct already
* initialized to 0, thus avoid resetting them)
*/
rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000080;
rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000;
rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000080;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
rstate->bo[0] = bo;
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
return -ENOMEM;
}
bstates->vs_resource0 = rstate;
rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 1);
rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 1);
if (rstate == NULL) {
return -ENOMEM;
}
rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000010;
rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000070;
rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000;
rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
@ -305,7 +303,7 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
}
radeon_bo_unmap(rscreen->rw, bo);
rstate = radeon_state(rscreen->rw, R600_VS_SHADER);
rstate = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
if (rstate == NULL) {
radeon_bo_decref(rscreen->rw, bo);
return NULL;
@ -323,8 +321,6 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
rstate->nbo = 2;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID;
rstate->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
@ -378,7 +374,7 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
}
radeon_bo_unmap(rscreen->rw, bo);
rstate = radeon_state(rscreen->rw, R600_PS_SHADER);
rstate = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
if (rstate == NULL) {
radeon_bo_decref(rscreen->rw, bo);
return NULL;
@ -395,7 +391,6 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
rstate->bo[0] = bo;
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
@ -408,7 +403,7 @@ static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_VGT);
rstate = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
if (rstate == NULL)
return NULL;
@ -430,7 +425,7 @@ static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_DRAW);
rstate = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
if (rstate == NULL)
return NULL;
@ -453,7 +448,7 @@ static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscr
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT0 + id);
rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT_TYPE, R600_VS_CONSTANT + id);
if (rstate == NULL)
return NULL;
@ -476,7 +471,7 @@ static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscre
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_RASTERIZER);
rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
if (rstate == NULL)
return NULL;
@ -505,7 +500,7 @@ static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_DSA);
rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
if (rstate == NULL)
return NULL;
@ -529,7 +524,7 @@ static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_BLEND);
rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
if (rstate == NULL)
return NULL;
@ -548,7 +543,7 @@ static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_CB_CNTL);
rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
if (rstate == NULL)
return NULL;
@ -791,10 +786,10 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
r600_queries_suspend(ctx);
/* schedule draw*/
r = radeon_ctx_set_draw(rctx->ctx, draw);
r = radeon_ctx_set_draw_new(rctx->ctx, draw);
if (r == -EBUSY) {
r600_flush(ctx, 0, NULL);
r = radeon_ctx_set_draw(rctx->ctx, draw);
r = radeon_ctx_set_draw_new(rctx->ctx, draw);
}
if (r) {
goto out;

9
src/gallium/drivers/r600/r600_context.c
View file

@ -53,10 +53,12 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
/* suspend queries */
r600_queries_suspend(ctx);
if (radeon_ctx_pm4(rctx->ctx))
goto out;
/* FIXME dumping should be removed once shader support instructions
* without throwing bad code
*/
if (!rctx->ctx->id)
if (!rctx->ctx->cpm4)
goto out;
sprintf(dname, "gallium-%08d.bof", dc);
if (dc < 2) {
@ -71,7 +73,8 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
}
dc++;
out:
radeon_ctx_clear(rctx->ctx);
rctx->ctx = radeon_ctx_decref(rctx->ctx);
rctx->ctx = radeon_ctx(rscreen->rw);
/* resume queries */
r600_queries_resume(ctx);
}
@ -215,7 +218,7 @@ static void r600_init_config(struct r600_context *rctx)
num_es_stack_entries = 0;
break;
}
rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG);
rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
switch (family) {

46
src/gallium/drivers/r600/r600_draw.c
View file

@ -101,21 +101,19 @@ static int r600_draw_common(struct r600_draw *draw)
rbuffer = (struct r600_resource*)vertex_buffer->buffer;
offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + i);
vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
if (vs_resource == NULL)
return -ENOMEM;
vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
vs_resource->nbo = 1;
vs_resource->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
vs_resource->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD0] = offset;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD1] = rbuffer->bo->size - offset;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
S_038008_DATA_FORMAT(format);
vs_resource->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
r = radeon_draw_set_new(rctx->draw, vs_resource);
@ -123,29 +121,22 @@ static int r600_draw_common(struct r600_draw *draw)
return r;
}
/* FIXME start need to change winsys */
draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
if (draw->draw == NULL)
return -ENOMEM;
draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
if (draw->index_buffer) {
draw->draw = radeon_state(rscreen->rw, R600_DRAW);
if (draw->draw == NULL)
return -ENOMEM;
draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
rbuffer = (struct r600_resource*)draw->index_buffer;
draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
draw->draw->nbo = 1;
draw->draw->reloc_pm4_id[0] = R600_DRAW__INDICES_BO_ID;
} else {
draw->draw = radeon_state(rscreen->rw, R600_DRAW_AUTO);
if (draw->draw == NULL)
return -ENOMEM;
draw->draw->states[R600_DRAW_AUTO__VGT_NUM_INDICES] = draw->count;
draw->draw->states[R600_DRAW_AUTO__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
}
r = radeon_draw_set_new(rctx->draw, draw->draw);
if (r)
return r;
draw->vgt = radeon_state(rscreen->rw, R600_VGT);
draw->vgt = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
if (draw->vgt == NULL)
return -ENOMEM;
draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
@ -154,18 +145,23 @@ static int r600_draw_common(struct r600_draw *draw)
draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
draw->vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
r = radeon_draw_set_new(rctx->draw, draw->vgt);
if (r)
return r;
/* FIXME */
r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
if (r == -EBUSY) {
r600_flush(draw->ctx, 0, NULL);
r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
}
if (r)
return r;
rctx->draw = radeon_draw_duplicate(rctx->draw);
return 0;
}

6
src/gallium/drivers/r600/r600_query.c
View file

@ -36,11 +36,10 @@ static struct radeon_state *r600_query_begin(struct r600_context *rctx, struct r
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN);
rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN_TYPE, R600_QUERY_BEGIN);
if (rstate == NULL)
return NULL;
rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
@ -56,11 +55,10 @@ static struct radeon_state *r600_query_end(struct r600_context *rctx, struct r60
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_QUERY_END);
rstate = radeon_state(rscreen->rw, R600_QUERY_END_TYPE, R600_QUERY_END);
if (rstate == NULL)
return NULL;
rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;

7
src/gallium/drivers/r600/r600_shader.c
View file

@ -132,7 +132,7 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
unsigned i, tmp;
rpshader->rstate = radeon_state_decref(rpshader->rstate);
state = radeon_state(rscreen->rw, R600_VS_SHADER);
state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
if (state == NULL)
return -ENOMEM;
for (i = 0; i < 10; i++) {
@ -152,8 +152,6 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
rpshader->rstate->nbo = 2;
rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rpshader->rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
state->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID;
state->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID;
return radeon_state_pm4(state);
}
@ -168,7 +166,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
rasterizer = &rctx->rasterizer->state.rasterizer;
rpshader->rstate = radeon_state_decref(rpshader->rstate);
state = radeon_state(rscreen->rw, R600_PS_SHADER);
state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
if (state == NULL)
return -ENOMEM;
for (i = 0; i < rshader->ninput; i++) {
@ -208,7 +206,6 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
rpshader->rstate->nbo = 1;
rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
state->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID;
return radeon_state_pm4(state);
}

78
src/gallium/drivers/r600/r600_state.c
View file

@ -283,17 +283,19 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
{
struct r600_screen *rscreen = r600_screen(ctx->screen);
struct r600_context *rctx = r600_context(ctx);
unsigned nconstant = 0, i, id;
unsigned nconstant = 0, i, type, id;
struct radeon_state *rstate;
struct pipe_transfer *transfer;
u32 *ptr;
switch (shader) {
case PIPE_SHADER_VERTEX:
id = R600_VS_CONSTANT0;
id = R600_VS_CONSTANT;
type = R600_VS_CONSTANT_TYPE;
break;
case PIPE_SHADER_FRAGMENT:
id = R600_PS_CONSTANT0;
id = R600_PS_CONSTANT;
type = R600_PS_CONSTANT_TYPE;
break;
default:
R600_ERR("unsupported %d\n", shader);
@ -305,7 +307,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
if (ptr == NULL)
return;
for (i = 0; i < nconstant; i++) {
rstate = radeon_state(rscreen->rw, id + i);
rstate = radeon_state(rscreen->rw, type, id + i);
if (rstate == NULL)
return;
rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
@ -620,7 +622,7 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
const struct pipe_blend_state *state = &rctx->blend->state.blend;
int i;
rstate = radeon_state(rscreen->rw, R600_BLEND);
rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
if (rstate == NULL)
return NULL;
rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
@ -679,14 +681,14 @@ static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip)
struct radeon_state *rstate;
const struct pipe_clip_state *state = &rctx->clip->state.clip;
rstate = radeon_state(rscreen->rw, R600_UCP0 + clip);
rstate = radeon_state(rscreen->rw, R600_CLIP_TYPE, R600_CLIP + clip);
if (rstate == NULL)
return NULL;
rstate->states[R600_UCP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
rstate->states[R600_UCP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
rstate->states[R600_UCP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
rstate->states[R600_UCP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
rstate->states[R600_CLIP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
rstate->states[R600_CLIP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
rstate->states[R600_CLIP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
rstate->states[R600_CLIP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
@ -709,7 +711,7 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
unsigned format, swap, ntype;
const struct util_format_description *desc;
rstate = radeon_state(rscreen->rw, R600_CB0 + cb);
rstate = radeon_state(rscreen->rw, R600_CB0_TYPE + cb, R600_CB0 + cb);
if (rstate == NULL)
return NULL;
rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
@ -720,9 +722,6 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
rstate->reloc_pm4_id[0] = R600_CB__CB_COLOR0_BASE_BO_ID;
rstate->reloc_pm4_id[1] = R600_CB__CB_COLOR0_FRAG_BO_ID;
rstate->reloc_pm4_id[2] = R600_CB__CB_COLOR0_TILE_BO_ID;
rstate->nbo = 3;
pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
@ -741,14 +740,14 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
S_0280A0_SOURCE_FORMAT(1) |
S_0280A0_NUMBER_TYPE(ntype);
rstate->states[R600_CB__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
rstate->states[R600_CB__CB_COLOR0_INFO] = color_info;
rstate->states[R600_CB__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
rstate->states[R600_CB0__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
S_028060_SLICE_TILE_MAX(slice);
rstate->states[R600_CB__CB_COLOR0_VIEW] = 0x00000000;
rstate->states[R600_CB__CB_COLOR0_FRAG] = 0x00000000;
rstate->states[R600_CB__CB_COLOR0_TILE] = 0x00000000;
rstate->states[R600_CB__CB_COLOR0_MASK] = 0x00000000;
rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
return NULL;
@ -769,7 +768,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
if (state->zsbuf == NULL)
return NULL;
rstate = radeon_state(rscreen->rw, R600_DB);
rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
if (rstate == NULL)
return NULL;
@ -783,7 +782,6 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
rstate->reloc_pm4_id[0] = R600_DB__DB_DEPTH_BASE_BO_ID;
level = state->zsbuf->level;
pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
@ -846,7 +844,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
prov_vtx = 0;
rctx->flat_shade = state->flatshade;
rstate = radeon_state(rscreen->rw, R600_RASTERIZER);
rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
if (rstate == NULL)
return NULL;
rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
@ -927,7 +925,7 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
}
tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
rstate = radeon_state(rscreen->rw, R600_SCISSOR);
rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
if (rstate == NULL)
return NULL;
rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
@ -962,7 +960,7 @@ static struct radeon_state *r600_viewport(struct r600_context *rctx)
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_VIEWPORT);
rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
if (rstate == NULL)
return NULL;
rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
@ -995,7 +993,7 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
if (rctx->ps_shader == NULL) {
return NULL;
}
rstate = radeon_state(rscreen->rw, R600_DSA);
rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
if (rstate == NULL)
return NULL;
@ -1147,7 +1145,7 @@ static struct radeon_state *r600_sampler(struct r600_context *rctx,
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, id);
rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
if (rstate == NULL)
return NULL;
rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
@ -1248,7 +1246,7 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
R600_ERR("unknow format %d\n", view->texture->format);
return NULL;
}
rstate = radeon_state(rscreen->rw, id);
rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
if (rstate == NULL) {
return NULL;
}
@ -1270,36 +1268,34 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
pitch = (tmp->pitch[0] / tmp->bpt);
pitch = (pitch + 0x7) & ~0x7;
/* FIXME properly handle first level != 0 */
rstate->states[R600_RESOURCE__RESOURCE_WORD0] =
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
S_038000_DIM(r600_tex_dim(view->texture->target)) |
S_038000_TILE_MODE(array_mode) |
S_038000_TILE_TYPE(tile_type) |
S_038000_PITCH((pitch / 8) - 1) |
S_038000_TEX_WIDTH(view->texture->width0 - 1);
rstate->states[R600_RESOURCE__RESOURCE_WORD1] =
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
S_038004_DATA_FORMAT(format);
rstate->states[R600_RESOURCE__RESOURCE_WORD2] = tmp->offset[0] >> 8;
rstate->states[R600_RESOURCE__RESOURCE_WORD3] = tmp->offset[1] >> 8;
rstate->states[R600_RESOURCE__RESOURCE_WORD4] =
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
word4 |
S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
S_038010_REQUEST_SIZE(1) |
S_038010_BASE_LEVEL(view->first_level);
rstate->states[R600_RESOURCE__RESOURCE_WORD5] =
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
S_038014_LAST_LEVEL(view->last_level) |
S_038014_BASE_ARRAY(0) |
S_038014_LAST_ARRAY(0);
rstate->states[R600_RESOURCE__RESOURCE_WORD6] =
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
@ -1346,7 +1342,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
target_mask |= (pbs->rt[0].colormask << (4 * i));
}
}
rstate = radeon_state(rscreen->rw, R600_CB_CNTL);
rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
@ -1423,7 +1419,7 @@ int r600_context_hw_states(struct pipe_context *ctx)
if (rctx->ps_sampler[i]) {
rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
&rctx->ps_sampler[i]->state.sampler,
R600_PS_SAMPLER0 + i);
R600_PS_SAMPLER + i);
}
}
rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
@ -1431,7 +1427,7 @@ int r600_context_hw_states(struct pipe_context *ctx)
if (rctx->ps_sampler_view[i]) {
rctx->hw_states.ps_resource[i] = r600_resource(ctx,
&rctx->ps_sampler_view[i]->state.sampler_view,
R600_PS_RESOURCE0 + i);
R600_PS_RESOURCE + i);
}
}
rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;

18
src/gallium/drivers/r600/r600_texture.c
View file

@ -663,7 +663,7 @@ static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscre
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_SCISSOR);
rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
if (rstate == NULL)
return NULL;
@ -707,7 +707,7 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
unsigned format, swap, ntype;
const struct util_format_description *desc;
rstate = radeon_state(rscreen->rw, R600_CB0);
rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
if (rstate == NULL)
return NULL;
rbuffer = &rtexture->resource;
@ -742,16 +742,13 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
rstate->nbo = 3;
color_info = S_0280A0_SOURCE_FORMAT(1);
}
rstate->reloc_pm4_id[0] = R600_CB__CB_COLOR0_BASE_BO_ID;
rstate->reloc_pm4_id[1] = R600_CB__CB_COLOR0_FRAG_BO_ID;
rstate->reloc_pm4_id[2] = R600_CB__CB_COLOR0_TILE_BO_ID;
color_info |= S_0280A0_FORMAT(format) |
S_0280A0_COMP_SWAP(swap) |
S_0280A0_BLEND_CLAMP(1) |
S_0280A0_NUMBER_TYPE(ntype);
rstate->states[R600_CB__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
rstate->states[R600_CB__CB_COLOR0_INFO] = color_info;
rstate->states[R600_CB__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
S_028060_SLICE_TILE_MAX(slice);
if (radeon_state_pm4(rstate)) {
@ -769,7 +766,7 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
struct r600_resource *rbuffer;
unsigned pitch, slice, format;
rstate = radeon_state(rscreen->rw, R600_DB);
rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
if (rstate == NULL)
return NULL;
rbuffer = &rtexture->resource;
@ -787,7 +784,6 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
S_028000_SLICE_TILE_MAX(slice);
rstate->reloc_pm4_id[0] = R600_DB__DB_DEPTH_BASE_BO_ID;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 1;
@ -819,7 +815,7 @@ static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscr
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_VIEWPORT);
rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
if (rstate == NULL)
return NULL;

669
src/gallium/drivers/r600/radeon.h
View file

@ -104,18 +104,26 @@ int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
struct radeon_state {
struct radeon *radeon;
unsigned refcount;
unsigned type;
unsigned id;
unsigned nstates;
u32 *states;
unsigned npm4;
unsigned cpm4;
u32 states[128];
u32 pm4_crc;
u32 *pm4;
u32 nimmd;
u32 *immd;
unsigned nbo;
struct radeon_bo *bo[4];
unsigned reloc_pm4_id[4];
unsigned nreloc;
unsigned reloc_pm4_id[8];
unsigned reloc_bo_id[8];
u32 placement[8];
unsigned bo_dirty[4];
};
struct radeon_state *radeon_state(struct radeon *radeon, u32 id);
struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id);
struct radeon_state *radeon_state_incref(struct radeon_state *state);
struct radeon_state *radeon_state_decref(struct radeon_state *state);
int radeon_state_pm4(struct radeon_state *state);
@ -139,6 +147,16 @@ int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state);
int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state);
int radeon_draw_check(struct radeon_draw *draw);
struct radeon_ctx *radeon_ctx(struct radeon *radeon);
struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
int radeon_ctx_pm4(struct radeon_ctx *ctx);
int radeon_ctx_submit(struct radeon_ctx *ctx);
void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
/*
* radeon context functions
*/
@ -151,216 +169,261 @@ struct radeon_cs_reloc {
};
#pragma pack()
struct radeon_ctx_bo {
struct radeon_bo *bo;
u32 bo_flushed;
unsigned state_id;
};
struct radeon_ctx {
int refcount;
struct radeon *radeon;
u32 *pm4;
int npm4;
u32 cpm4;
u32 draw_cpm4;
unsigned id;
unsigned next_id;
unsigned nreloc;
unsigned max_reloc;
struct radeon_cs_reloc *reloc;
unsigned nbo;
struct radeon_ctx_bo *bo;
unsigned max_bo;
u32 *state_crc32;
struct radeon_bo **bo;
unsigned ndraw;
struct radeon_draw *cdraw;
struct radeon_draw **draw;
unsigned nstate;
struct radeon_state **state;
};
struct radeon_ctx *radeon_ctx(struct radeon *radeon);
struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
void radeon_ctx_clear(struct radeon_ctx *ctx);
int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
int radeon_ctx_pm4(struct radeon_ctx *ctx);
int radeon_ctx_submit(struct radeon_ctx *ctx);
void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
/*
* R600/R700
*/
#define R600_CONFIG 0
#define R600_CB_CNTL 1
#define R600_RASTERIZER 2
#define R600_VIEWPORT 3
#define R600_SCISSOR 4
#define R600_BLEND 5
#define R600_DSA 6
#define R600_VGT 7
#define R600_QUERY_BEGIN 8
#define R600_QUERY_END 9
#define R600_VS_SHADER 10
#define R600_PS_SHADER 11
#define R600_DB 12
#define R600_CB0 13
#define R600_UCP0 21
#define R600_PS_RESOURCE0 27
#define R600_VS_RESOURCE0 187
#define R600_FS_RESOURCE0 347
#define R600_GS_RESOURCE0 363
#define R600_PS_CONSTANT0 523
#define R600_VS_CONSTANT0 779
#define R600_PS_SAMPLER0 1035
#define R600_VS_SAMPLER0 1053
#define R600_GS_SAMPLER0 1071
#define R600_PS_SAMPLER_BORDER0 1089
#define R600_VS_SAMPLER_BORDER0 1107
#define R600_GS_SAMPLER_BORDER0 1125
#define R600_DRAW_AUTO 1143
#define R600_DRAW 1144
#define R600_NSTATE 1145
#define R600_NSTATE 1288
#define R600_NTYPE 35
#define R600_CONFIG 0
#define R600_CONFIG_TYPE 0
#define R600_CB_CNTL 1
#define R600_CB_CNTL_TYPE 1
#define R600_RASTERIZER 2
#define R600_RASTERIZER_TYPE 2
#define R600_VIEWPORT 3
#define R600_VIEWPORT_TYPE 3
#define R600_SCISSOR 4
#define R600_SCISSOR_TYPE 4
#define R600_BLEND 5
#define R600_BLEND_TYPE 5
#define R600_DSA 6
#define R600_DSA_TYPE 6
#define R600_VS_SHADER 7
#define R600_VS_SHADER_TYPE 7
#define R600_PS_SHADER 8
#define R600_PS_SHADER_TYPE 8
#define R600_PS_CONSTANT 9
#define R600_PS_CONSTANT_TYPE 9
#define R600_VS_CONSTANT 265
#define R600_VS_CONSTANT_TYPE 10
#define R600_PS_RESOURCE 521
#define R600_PS_RESOURCE_TYPE 11
#define R600_VS_RESOURCE 681
#define R600_VS_RESOURCE_TYPE 12
#define R600_FS_RESOURCE 841
#define R600_FS_RESOURCE_TYPE 13
#define R600_GS_RESOURCE 1001
#define R600_GS_RESOURCE_TYPE 14
#define R600_PS_SAMPLER 1161
#define R600_PS_SAMPLER_TYPE 15
#define R600_VS_SAMPLER 1179
#define R600_VS_SAMPLER_TYPE 16
#define R600_GS_SAMPLER 1197
#define R600_GS_SAMPLER_TYPE 17
#define R600_PS_SAMPLER_BORDER 1215
#define R600_PS_SAMPLER_BORDER_TYPE 18
#define R600_VS_SAMPLER_BORDER 1233
#define R600_VS_SAMPLER_BORDER_TYPE 19
#define R600_GS_SAMPLER_BORDER 1251
#define R600_GS_SAMPLER_BORDER_TYPE 20
#define R600_CB0 1269
#define R600_CB0_TYPE 21
#define R600_CB1 1270
#define R600_CB1_TYPE 22
#define R600_CB2 1271
#define R600_CB2_TYPE 23
#define R600_CB3 1272
#define R600_CB3_TYPE 24
#define R600_CB4 1273
#define R600_CB4_TYPE 25
#define R600_CB5 1274
#define R600_CB5_TYPE 26
#define R600_CB6 1275
#define R600_CB6_TYPE 27
#define R600_CB7 1276
#define R600_CB7_TYPE 28
#define R600_QUERY_BEGIN 1277
#define R600_QUERY_BEGIN_TYPE 29
#define R600_QUERY_END 1278
#define R600_QUERY_END_TYPE 30
#define R600_DB 1279
#define R600_DB_TYPE 31
#define R600_CLIP 1280
#define R600_CLIP_TYPE 32
#define R600_VGT 1286
#define R600_VGT_TYPE 33
#define R600_DRAW 1287
#define R600_DRAW_TYPE 34
/* R600_CONFIG */
#define R600_CONFIG__SQ_CONFIG 0
#define R600_CONFIG__SQ_CONFIG 0
#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1 1
#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2 2
#define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT 3
#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1 4
#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2 5
#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 8
#define R600_CONFIG__TA_CNTL_AUX 11
#define R600_CONFIG__VC_ENHANCE 14
#define R600_CONFIG__DB_DEBUG 17
#define R600_CONFIG__DB_WATERMARKS 20
#define R600_CONFIG__SX_MISC 23
#define R600_CONFIG__SPI_THREAD_GROUPING 26
#define R600_CONFIG__CB_SHADER_CONTROL 29
#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 32
#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 33
#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 34
#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 35
#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 36
#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 37
#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 38
#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 39
#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 40
#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 43
#define R600_CONFIG__VGT_HOS_CNTL 44
#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 45
#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 46
#define R600_CONFIG__VGT_HOS_REUSE_DEPTH 47
#define R600_CONFIG__VGT_GROUP_PRIM_TYPE 48
#define R600_CONFIG__VGT_GROUP_FIRST_DECR 49
#define R600_CONFIG__VGT_GROUP_DECR 50
#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 51
#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 52
#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 53
#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 54
#define R600_CONFIG__VGT_GS_MODE 55
#define R600_CONFIG__PA_SC_MODE_CNTL 58
#define R600_CONFIG__VGT_STRMOUT_EN 61
#define R600_CONFIG__VGT_REUSE_OFF 62
#define R600_CONFIG__VGT_VTX_CNT_EN 63
#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 66
#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 6
#define R600_CONFIG__TA_CNTL_AUX 7
#define R600_CONFIG__VC_ENHANCE 8
#define R600_CONFIG__DB_DEBUG 9
#define R600_CONFIG__DB_WATERMARKS 10
#define R600_CONFIG__SX_MISC 11
#define R600_CONFIG__SPI_THREAD_GROUPING 12
#define R600_CONFIG__CB_SHADER_CONTROL 13
#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 14
#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 15
#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 16
#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 17
#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 18
#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 19
#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 20
#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 21
#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 22
#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 23
#define R600_CONFIG__VGT_HOS_CNTL 24
#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 25
#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 26
#define R600_CONFIG__VGT_HOS_REUSE_DEPTH 27
#define R600_CONFIG__VGT_GROUP_PRIM_TYPE 28
#define R600_CONFIG__VGT_GROUP_FIRST_DECR 29
#define R600_CONFIG__VGT_GROUP_DECR 30
#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 31
#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 32
#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 33
#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 34
#define R600_CONFIG__VGT_GS_MODE 35
#define R600_CONFIG__PA_SC_MODE_CNTL 36
#define R600_CONFIG__VGT_STRMOUT_EN 37
#define R600_CONFIG__VGT_REUSE_OFF 38
#define R600_CONFIG__VGT_VTX_CNT_EN 39
#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 40
#define R600_CONFIG_SIZE 41
#define R600_CONFIG_PM4 128
/* R600_CB_CNTL */
#define R600_CB_CNTL__CB_CLEAR_RED 0
#define R600_CB_CNTL__CB_CLEAR_GREEN 1
#define R600_CB_CNTL__CB_CLEAR_BLUE 2
#define R600_CB_CNTL__CB_CLEAR_ALPHA 3
#define R600_CB_CNTL__CB_SHADER_MASK 6
#define R600_CB_CNTL__CB_TARGET_MASK 7
#define R600_CB_CNTL__CB_FOG_RED 10
#define R600_CB_CNTL__CB_FOG_GREEN 11
#define R600_CB_CNTL__CB_FOG_BLUE 12
#define R600_CB_CNTL__CB_COLOR_CONTROL 15
#define R600_CB_CNTL__PA_SC_AA_CONFIG 18
#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 21
#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 22
#define R600_CB_CNTL__CB_CLRCMP_CONTROL 25
#define R600_CB_CNTL__CB_CLRCMP_SRC 26
#define R600_CB_CNTL__CB_CLRCMP_DST 27
#define R600_CB_CNTL__CB_CLRCMP_MSK 28
#define R600_CB_CNTL__PA_SC_AA_MASK 31
#define R600_CB_CNTL__CB_CLEAR_RED 0
#define R600_CB_CNTL__CB_CLEAR_GREEN 1
#define R600_CB_CNTL__CB_CLEAR_BLUE 2
#define R600_CB_CNTL__CB_CLEAR_ALPHA 3
#define R600_CB_CNTL__CB_SHADER_MASK 4
#define R600_CB_CNTL__CB_TARGET_MASK 5
#define R600_CB_CNTL__CB_FOG_RED 6
#define R600_CB_CNTL__CB_FOG_GREEN 7
#define R600_CB_CNTL__CB_FOG_BLUE 8
#define R600_CB_CNTL__CB_COLOR_CONTROL 9
#define R600_CB_CNTL__PA_SC_AA_CONFIG 10
#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 11
#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 12
#define R600_CB_CNTL__CB_CLRCMP_CONTROL 13
#define R600_CB_CNTL__CB_CLRCMP_SRC 14
#define R600_CB_CNTL__CB_CLRCMP_DST 15
#define R600_CB_CNTL__CB_CLRCMP_MSK 16
#define R600_CB_CNTL__PA_SC_AA_MASK 17
#define R600_CB_CNTL_SIZE 18
#define R600_CB_CNTL_PM4 128
/* R600_RASTERIZER */
#define R600_RASTERIZER__SPI_INTERP_CONTROL_0 0
#define R600_RASTERIZER__PA_CL_CLIP_CNTL 3
#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL 4
#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL 7
#define R600_RASTERIZER__PA_CL_NANINF_CNTL 8
#define R600_RASTERIZER__PA_SU_POINT_SIZE 11
#define R600_RASTERIZER__PA_SU_POINT_MINMAX 12
#define R600_RASTERIZER__PA_SU_LINE_CNTL 13
#define R600_RASTERIZER__PA_SC_LINE_STIPPLE 14
#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL 17
#define R600_RASTERIZER__PA_SC_LINE_CNTL 20
#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 23
#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 24
#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 25
#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 26
#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 29
#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 30
#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 31
#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 32
#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 33
#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 34
#define R600_RASTERIZER__PA_CL_CLIP_CNTL 1
#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL 2
#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL 3
#define R600_RASTERIZER__PA_CL_NANINF_CNTL 4
#define R600_RASTERIZER__PA_SU_POINT_SIZE 5
#define R600_RASTERIZER__PA_SU_POINT_MINMAX 6
#define R600_RASTERIZER__PA_SU_LINE_CNTL 7
#define R600_RASTERIZER__PA_SC_LINE_STIPPLE 8
#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL 9
#define R600_RASTERIZER__PA_SC_LINE_CNTL 10
#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 11
#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 12
#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 13
#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 14
#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 15
#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 16
#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 17
#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 18
#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 19
#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 20
#define R600_RASTERIZER_SIZE 21
#define R600_RASTERIZER_PM4 128
/* R600_VIEWPORT */
#define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0 0
#define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0 1
#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0 4
#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0 7
#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0 10
#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0 13
#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0 16
#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 19
#define R600_VIEWPORT__PA_CL_VTE_CNTL 22
#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0 2
#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0 3
#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0 4
#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0 5
#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0 6
#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 7
#define R600_VIEWPORT__PA_CL_VTE_CNTL 8
#define R600_VIEWPORT_SIZE 9
#define R600_VIEWPORT_PM4 128
/* R600_SCISSOR */
#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL 0
#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR 1
#define R600_SCISSOR__PA_SC_WINDOW_OFFSET 4
#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 5
#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 6
#define R600_SCISSOR__PA_SC_CLIPRECT_RULE 7
#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL 8
#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR 9
#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL 10
#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR 11
#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL 12
#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR 13
#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL 14
#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR 15
#define R600_SCISSOR__PA_SC_EDGERULE 16
#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 19
#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 20
#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 23
#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 24
#define R600_SCISSOR__PA_SC_WINDOW_OFFSET 2
#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 3
#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 4
#define R600_SCISSOR__PA_SC_CLIPRECT_RULE 5
#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL 6
#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR 7
#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL 8
#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR 9
#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL 10
#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR 11
#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL 12
#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR 13
#define R600_SCISSOR__PA_SC_EDGERULE 14
#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 15
#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 16
#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 17
#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 18
#define R600_SCISSOR_SIZE 19
#define R600_SCISSOR_PM4 128
/* R600_BLEND */
#define R600_BLEND__CB_BLEND_RED 0
#define R600_BLEND__CB_BLEND_GREEN 1
#define R600_BLEND__CB_BLEND_BLUE 2
#define R600_BLEND__CB_BLEND_ALPHA 3
#define R600_BLEND__CB_BLEND0_CONTROL 6
#define R600_BLEND__CB_BLEND1_CONTROL 7
#define R600_BLEND__CB_BLEND2_CONTROL 8
#define R600_BLEND__CB_BLEND3_CONTROL 9
#define R600_BLEND__CB_BLEND4_CONTROL 10
#define R600_BLEND__CB_BLEND5_CONTROL 11
#define R600_BLEND__CB_BLEND6_CONTROL 12
#define R600_BLEND__CB_BLEND7_CONTROL 13
#define R600_BLEND__CB_BLEND_CONTROL 16
#define R600_BLEND__CB_BLEND_RED 0
#define R600_BLEND__CB_BLEND_GREEN 1
#define R600_BLEND__CB_BLEND_BLUE 2
#define R600_BLEND__CB_BLEND_ALPHA 3
#define R600_BLEND__CB_BLEND0_CONTROL 4
#define R600_BLEND__CB_BLEND1_CONTROL 5
#define R600_BLEND__CB_BLEND2_CONTROL 6
#define R600_BLEND__CB_BLEND3_CONTROL 7
#define R600_BLEND__CB_BLEND4_CONTROL 8
#define R600_BLEND__CB_BLEND5_CONTROL 9
#define R600_BLEND__CB_BLEND6_CONTROL 10
#define R600_BLEND__CB_BLEND7_CONTROL 11
#define R600_BLEND__CB_BLEND_CONTROL 12
#define R600_BLEND_SIZE 13
#define R600_BLEND_PM4 128
/* R600_DSA */
#define R600_DSA__DB_STENCIL_CLEAR 0
#define R600_DSA__DB_DEPTH_CLEAR 1
#define R600_DSA__SX_ALPHA_TEST_CONTROL 4
#define R600_DSA__DB_STENCILREFMASK 7
#define R600_DSA__DB_STENCILREFMASK_BF 8
#define R600_DSA__SX_ALPHA_REF 9
#define R600_DSA__SPI_FOG_FUNC_SCALE 12
#define R600_DSA__SPI_FOG_FUNC_BIAS 13
#define R600_DSA__SPI_FOG_CNTL 16
#define R600_DSA__DB_DEPTH_CONTROL 19
#define R600_DSA__DB_SHADER_CONTROL 22
#define R600_DSA__DB_RENDER_CONTROL 25
#define R600_DSA__DB_RENDER_OVERRIDE 26
#define R600_DSA__DB_SRESULTS_COMPARE_STATE1 29
#define R600_DSA__DB_PRELOAD_CONTROL 30
#define R600_DSA__DB_ALPHA_TO_MASK 33
#define R600_DSA__DB_STENCIL_CLEAR 0
#define R600_DSA__DB_DEPTH_CLEAR 1
#define R600_DSA__SX_ALPHA_TEST_CONTROL 2
#define R600_DSA__DB_STENCILREFMASK 3
#define R600_DSA__DB_STENCILREFMASK_BF 4
#define R600_DSA__SX_ALPHA_REF 5
#define R600_DSA__SPI_FOG_FUNC_SCALE 6
#define R600_DSA__SPI_FOG_FUNC_BIAS 7
#define R600_DSA__SPI_FOG_CNTL 8
#define R600_DSA__DB_DEPTH_CONTROL 9
#define R600_DSA__DB_SHADER_CONTROL 10
#define R600_DSA__DB_RENDER_CONTROL 11
#define R600_DSA__DB_RENDER_OVERRIDE 12
#define R600_DSA__DB_SRESULTS_COMPARE_STATE1 13
#define R600_DSA__DB_PRELOAD_CONTROL 14
#define R600_DSA__DB_ALPHA_TO_MASK 15
#define R600_DSA_SIZE 16
#define R600_DSA_PM4 128
/* R600_VS_SHADER */
#define R600_VS_SHADER__SQ_VTX_SEMANTIC_0 0
#define R600_VS_SHADER__SQ_VTX_SEMANTIC_1 1
@ -394,25 +457,25 @@ void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
#define R600_VS_SHADER__SQ_VTX_SEMANTIC_29 29
#define R600_VS_SHADER__SQ_VTX_SEMANTIC_30 30
#define R600_VS_SHADER__SQ_VTX_SEMANTIC_31 31
#define R600_VS_SHADER__SPI_VS_OUT_ID_0 34
#define R600_VS_SHADER__SPI_VS_OUT_ID_1 35
#define R600_VS_SHADER__SPI_VS_OUT_ID_2 36
#define R600_VS_SHADER__SPI_VS_OUT_ID_3 37
#define R600_VS_SHADER__SPI_VS_OUT_ID_4 38
#define R600_VS_SHADER__SPI_VS_OUT_ID_5 39
#define R600_VS_SHADER__SPI_VS_OUT_ID_6 40
#define R600_VS_SHADER__SPI_VS_OUT_ID_7 41
#define R600_VS_SHADER__SPI_VS_OUT_ID_8 42
#define R600_VS_SHADER__SPI_VS_OUT_ID_9 43
#define R600_VS_SHADER__SPI_VS_OUT_CONFIG 46
#define R600_VS_SHADER__SQ_PGM_START_VS 49
#define R600_VS_SHADER__SQ_PGM_START_VS_BO_ID 51
#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS 54
#define R600_VS_SHADER__SQ_PGM_START_FS 57
#define R600_VS_SHADER__SQ_PGM_START_FS_BO_ID 59
#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS 62
#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS 65
#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS 68
#define R600_VS_SHADER__SPI_VS_OUT_ID_0 32
#define R600_VS_SHADER__SPI_VS_OUT_ID_1 33
#define R600_VS_SHADER__SPI_VS_OUT_ID_2 34
#define R600_VS_SHADER__SPI_VS_OUT_ID_3 35
#define R600_VS_SHADER__SPI_VS_OUT_ID_4 36
#define R600_VS_SHADER__SPI_VS_OUT_ID_5 37
#define R600_VS_SHADER__SPI_VS_OUT_ID_6 38
#define R600_VS_SHADER__SPI_VS_OUT_ID_7 39
#define R600_VS_SHADER__SPI_VS_OUT_ID_8 40
#define R600_VS_SHADER__SPI_VS_OUT_ID_9 41
#define R600_VS_SHADER__SPI_VS_OUT_CONFIG 42
#define R600_VS_SHADER__SQ_PGM_START_VS 43
#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS 44
#define R600_VS_SHADER__SQ_PGM_START_FS 45
#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS 46
#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS 47
#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS 48
#define R600_VS_SHADER_SIZE 49
#define R600_VS_SHADER_PM4 128
/* R600_PS_SHADER */
#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 0
#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1 1
@ -446,104 +509,158 @@ void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29 29
#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30 30
#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31 31
#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0 34
#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1 35
#define R600_PS_SHADER__SPI_INPUT_Z 38
#define R600_PS_SHADER__SQ_PGM_START_PS 41
#define R600_PS_SHADER__SQ_PGM_START_PS_BO_ID 43
#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS 46
#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS 47
#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS 50
#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0 32
#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1 33
#define R600_PS_SHADER__SPI_INPUT_Z 34
#define R600_PS_SHADER__SQ_PGM_START_PS 35
#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS 36
#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS 37
#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS 38
#define R600_PS_SHADER_SIZE 39
#define R600_PS_SHADER_PM4 128
/* R600_PS_CONSTANT */
#define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0 0
#define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0 1
#define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0 2
#define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0 3
#define R600_PS_CONSTANT_SIZE 4
#define R600_PS_CONSTANT_PM4 128
/* R600_VS_CONSTANT */
#define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256 0
#define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256 1
#define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256 2
#define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256 3
#define R600_VS_CONSTANT_SIZE 4
#define R600_VS_CONSTANT_PM4 128
/* R600_PS_RESOURCE */
#define R600_RESOURCE__RESOURCE_WORD0 0
#define R600_RESOURCE__RESOURCE_WORD1 1
#define R600_RESOURCE__RESOURCE_WORD2 2
#define R600_RESOURCE__RESOURCE_WORD3 3
#define R600_RESOURCE__RESOURCE_WORD4 4
#define R600_RESOURCE__RESOURCE_WORD5 5
#define R600_RESOURCE__RESOURCE_WORD6 6
#define R600_RESOURCE__RESOURCE_BO0_ID 8
#define R600_RESOURCE__RESOURCE_BO1_ID 10
#define R600_PS_RESOURCE__RESOURCE0_WORD0 0
#define R600_PS_RESOURCE__RESOURCE0_WORD1 1
#define R600_PS_RESOURCE__RESOURCE0_WORD2 2
#define R600_PS_RESOURCE__RESOURCE0_WORD3 3
#define R600_PS_RESOURCE__RESOURCE0_WORD4 4
#define R600_PS_RESOURCE__RESOURCE0_WORD5 5
#define R600_PS_RESOURCE__RESOURCE0_WORD6 6
#define R600_PS_RESOURCE_SIZE 7
#define R600_PS_RESOURCE_PM4 128
/* R600_VS_RESOURCE */
#define R600_VS_RESOURCE__RESOURCE160_WORD0 0
#define R600_VS_RESOURCE__RESOURCE160_WORD1 1
#define R600_VS_RESOURCE__RESOURCE160_WORD2 2
#define R600_VS_RESOURCE__RESOURCE160_WORD3 3
#define R600_VS_RESOURCE__RESOURCE160_WORD4 4
#define R600_VS_RESOURCE__RESOURCE160_WORD5 5
#define R600_VS_RESOURCE__RESOURCE160_WORD6 6
#define R600_VS_RESOURCE_SIZE 7
#define R600_VS_RESOURCE_PM4 128
/* R600_FS_RESOURCE */
#define R600_FS_RESOURCE__RESOURCE320_WORD0 0
#define R600_FS_RESOURCE__RESOURCE320_WORD1 1
#define R600_FS_RESOURCE__RESOURCE320_WORD2 2
#define R600_FS_RESOURCE__RESOURCE320_WORD3 3
#define R600_FS_RESOURCE__RESOURCE320_WORD4 4
#define R600_FS_RESOURCE__RESOURCE320_WORD5 5
#define R600_FS_RESOURCE__RESOURCE320_WORD6 6
#define R600_FS_RESOURCE_SIZE 7
#define R600_FS_RESOURCE_PM4 128
/* R600_GS_RESOURCE */
#define R600_GS_RESOURCE__RESOURCE336_WORD0 0
#define R600_GS_RESOURCE__RESOURCE336_WORD1 1
#define R600_GS_RESOURCE__RESOURCE336_WORD2 2
#define R600_GS_RESOURCE__RESOURCE336_WORD3 3
#define R600_GS_RESOURCE__RESOURCE336_WORD4 4
#define R600_GS_RESOURCE__RESOURCE336_WORD5 5
#define R600_GS_RESOURCE__RESOURCE336_WORD6 6
#define R600_GS_RESOURCE_SIZE 7
#define R600_GS_RESOURCE_PM4 128
/* R600_PS_SAMPLER */
#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0 0
#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0 1
#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0 2
#define R600_PS_SAMPLER_SIZE 3
#define R600_PS_SAMPLER_PM4 128
/* R600_VS_SAMPLER */
#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0
#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1
#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2
#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0
#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1
#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2
#define R600_VS_SAMPLER_SIZE 3
#define R600_VS_SAMPLER_PM4 128
/* R600_GS_SAMPLER */
#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0
#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1
#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2
#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0
#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1
#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2
#define R600_GS_SAMPLER_SIZE 3
#define R600_GS_SAMPLER_PM4 128
/* R600_PS_SAMPLER_BORDER */
#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0
#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1
#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2
#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3
#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0
#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1
#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2
#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3
#define R600_PS_SAMPLER_BORDER_SIZE 4
#define R600_PS_SAMPLER_BORDER_PM4 128
/* R600_VS_SAMPLER_BORDER */
#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0
#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1
#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2
#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3
#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0
#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1
#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2
#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3
#define R600_VS_SAMPLER_BORDER_SIZE 4
#define R600_VS_SAMPLER_BORDER_PM4 128
/* R600_GS_SAMPLER_BORDER */
#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0
#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1
#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2
#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3
/* R600_CB */
#define R600_CB__CB_COLOR0_BASE 0
#define R600_CB__CB_COLOR0_BASE_BO_ID 2
#define R600_CB__CB_COLOR0_INFO 5
#define R600_CB__CB_COLOR0_SIZE 8
#define R600_CB__CB_COLOR0_VIEW 11
#define R600_CB__CB_COLOR0_FRAG 14
#define R600_CB__CB_COLOR0_FRAG_BO_ID 16
#define R600_CB__CB_COLOR0_TILE 19
#define R600_CB__CB_COLOR0_TILE_BO_ID 21
#define R600_CB__CB_COLOR0_MASK 24
#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0
#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1
#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2
#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3
#define R600_GS_SAMPLER_BORDER_SIZE 4
#define R600_GS_SAMPLER_BORDER_PM4 128
/* R600_CB0 */
#define R600_CB0__CB_COLOR0_BASE 0
#define R600_CB0__CB_COLOR0_INFO 1
#define R600_CB0__CB_COLOR0_SIZE 2
#define R600_CB0__CB_COLOR0_VIEW 3
#define R600_CB0__CB_COLOR0_FRAG 4
#define R600_CB0__CB_COLOR0_TILE 5
#define R600_CB0__CB_COLOR0_MASK 6
#define R600_CB0_SIZE 7
#define R600_CB0_PM4 128
/* R600_DB */
#define R600_DB__DB_DEPTH_BASE 0
#define R600_DB__DB_DEPTH_BASE_BO_ID 2
#define R600_DB__DB_DEPTH_SIZE 5
#define R600_DB__DB_DEPTH_VIEW 6
#define R600_DB__DB_DEPTH_INFO 9
#define R600_DB__DB_HTILE_SURFACE 12
#define R600_DB__DB_PREFETCH_LIMIT 15
#define R600_DB__DB_DEPTH_BASE 0
#define R600_DB__DB_DEPTH_SIZE 1
#define R600_DB__DB_DEPTH_VIEW 2
#define R600_DB__DB_DEPTH_INFO 3
#define R600_DB__DB_HTILE_SURFACE 4
#define R600_DB__DB_PREFETCH_LIMIT 5
#define R600_DB_SIZE 6
#define R600_DB_PM4 128
/* R600_VGT */
#define R600_VGT__VGT_MAX_VTX_INDX 0
#define R600_VGT__VGT_MIN_VTX_INDX 1
#define R600_VGT__VGT_INDX_OFFSET 2
#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX 3
#define R600_VGT__VGT_PRIMITIVE_TYPE 6
#define R600_VGT__VGT_DMA_INDEX_TYPE 8
#define R600_VGT__VGT_DMA_NUM_INSTANCES 10
/* R600_DRAW_AUTO */
#define R600_DRAW_AUTO__VGT_NUM_INDICES 0
#define R600_DRAW_AUTO__VGT_DRAW_INITIATOR 1
#define R600_VGT__VGT_PRIMITIVE_TYPE 0
#define R600_VGT__VGT_MAX_VTX_INDX 1
#define R600_VGT__VGT_MIN_VTX_INDX 2
#define R600_VGT__VGT_INDX_OFFSET 3
#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX 4
#define R600_VGT__VGT_DMA_INDEX_TYPE 5
#define R600_VGT__VGT_PRIMITIVEID_EN 6
#define R600_VGT__VGT_DMA_NUM_INSTANCES 7
#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN 8
#define R600_VGT__VGT_INSTANCE_STEP_RATE_0 9
#define R600_VGT__VGT_INSTANCE_STEP_RATE_1 10
#define R600_VGT_SIZE 11
#define R600_VGT_PM4 128
/* R600_DRAW */
#define R600_DRAW__VGT_DMA_BASE 0
#define R600_DRAW__VGT_DMA_BASE_HI 1
#define R600_DRAW__VGT_NUM_INDICES 2
#define R600_DRAW__VGT_DRAW_INITIATOR 3
#define R600_DRAW__INDICES_BO_ID 5
/* R600_UCP */
#define R600_UCP__PA_CL_UCP_X_0 0
#define R600_UCP__PA_CL_UCP_Y_0 1
#define R600_UCP__PA_CL_UCP_Z_0 2
#define R600_UCP__PA_CL_UCP_W_0 3
#define R600_DRAW__VGT_NUM_INDICES 0
#define R600_DRAW__VGT_DMA_BASE_HI 1
#define R600_DRAW__VGT_DMA_BASE 2
#define R600_DRAW__VGT_DRAW_INITIATOR 3
#define R600_DRAW_SIZE 4
#define R600_DRAW_PM4 128
/* R600_CLIP */
#define R600_CLIP__PA_CL_UCP_X_0 0
#define R600_CLIP__PA_CL_UCP_Y_0 1
#define R600_CLIP__PA_CL_UCP_Z_0 2
#define R600_CLIP__PA_CL_UCP_W_0 3
#define R600_CLIP_SIZE 4
#define R600_CLIP_PM4 128
/* R600 QUERY BEGIN/END */
#define R600_QUERY__OFFSET 0
#define R600_QUERY__BO_ID 3
#define R600_QUERY__OFFSET 0
#define R600_QUERY_SIZE 1
#define R600_QUERY_PM4 128
#endif

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/*
* Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef R600_STATES_H
#define R600_STATES_H
static const struct radeon_register R600_CONFIG_names[] = {
{0x00008C00, 0, 0, "SQ_CONFIG"},
{0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"},
{0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"},
{0x00008C0C, 0, 0, "SQ_THREAD_RESOURCE_MGMT"},
{0x00008C10, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"},
{0x00008C14, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"},
{0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"},
{0x00009508, 0, 0, "TA_CNTL_AUX"},
{0x00009714, 0, 0, "VC_ENHANCE"},
{0x00009830, 0, 0, "DB_DEBUG"},
{0x00009838, 0, 0, "DB_WATERMARKS"},
{0x00028350, 0, 0, "SX_MISC"},
{0x000286C8, 0, 0, "SPI_THREAD_GROUPING"},
{0x000287A0, 0, 0, "CB_SHADER_CONTROL"},
{0x000288A8, 0, 0, "SQ_ESGS_RING_ITEMSIZE"},
{0x000288AC, 0, 0, "SQ_GSVS_RING_ITEMSIZE"},
{0x000288B0, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"},
{0x000288B4, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"},
{0x000288B8, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"},
{0x000288BC, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"},
{0x000288C0, 0, 0, "SQ_FBUF_RING_ITEMSIZE"},
{0x000288C4, 0, 0, "SQ_REDUC_RING_ITEMSIZE"},
{0x000288C8, 0, 0, "SQ_GS_VERT_ITEMSIZE"},
{0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"},
{0x00028A14, 0, 0, "VGT_HOS_CNTL"},
{0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"},
{0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"},
{0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"},
{0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"},
{0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"},
{0x00028A2C, 0, 0, "VGT_GROUP_DECR"},
{0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"},
{0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"},
{0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"},
{0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"},
{0x00028A40, 0, 0, "VGT_GS_MODE"},
{0x00028A4C, 0, 0, "PA_SC_MODE_CNTL"},
{0x00028AB0, 0, 0, "VGT_STRMOUT_EN"},
{0x00028AB4, 0, 0, "VGT_REUSE_OFF"},
{0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"},
{0x00028B20, 0, 0, "VGT_STRMOUT_BUFFER_EN"},
};
static const struct radeon_register R600_CB_CNTL_names[] = {
{0x00028120, 0, 0, "CB_CLEAR_RED"},
{0x00028124, 0, 0, "CB_CLEAR_GREEN"},
{0x00028128, 0, 0, "CB_CLEAR_BLUE"},
{0x0002812C, 0, 0, "CB_CLEAR_ALPHA"},
{0x0002823C, 0, 0, "CB_SHADER_MASK"},
{0x00028238, 0, 0, "CB_TARGET_MASK"},
{0x00028424, 0, 0, "CB_FOG_RED"},
{0x00028428, 0, 0, "CB_FOG_GREEN"},
{0x0002842C, 0, 0, "CB_FOG_BLUE"},
{0x00028808, 0, 0, "CB_COLOR_CONTROL"},
{0x00028C04, 0, 0, "PA_SC_AA_CONFIG"},
{0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"},
{0x00028C20, 0, 0, "PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX"},
{0x00028C30, 0, 0, "CB_CLRCMP_CONTROL"},
{0x00028C34, 0, 0, "CB_CLRCMP_SRC"},
{0x00028C38, 0, 0, "CB_CLRCMP_DST"},
{0x00028C3C, 0, 0, "CB_CLRCMP_MSK"},
{0x00028C48, 0, 0, "PA_SC_AA_MASK"},
};
static const struct radeon_register R600_RASTERIZER_names[] = {
{0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"},
{0x00028810, 0, 0, "PA_CL_CLIP_CNTL"},
{0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"},
{0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"},
{0x00028820, 0, 0, "PA_CL_NANINF_CNTL"},
{0x00028A00, 0, 0, "PA_SU_POINT_SIZE"},
{0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"},
{0x00028A08, 0, 0, "PA_SU_LINE_CNTL"},
{0x00028A0C, 0, 0, "PA_SC_LINE_STIPPLE"},
{0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"},
{0x00028C00, 0, 0, "PA_SC_LINE_CNTL"},
{0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"},
{0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"},
{0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"},
{0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"},
{0x00028DF8, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"},
{0x00028DFC, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"},
{0x00028E00, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"},
{0x00028E04, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"},
{0x00028E08, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"},
{0x00028E0C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"},
};
static const struct radeon_register R600_VIEWPORT_names[] = {
{0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"},
{0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"},
{0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"},
{0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"},
{0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"},
{0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"},
{0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"},
{0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"},
{0x00028818, 0, 0, "PA_CL_VTE_CNTL"},
};
static const struct radeon_register R600_SCISSOR_names[] = {
{0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"},
{0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"},
{0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"},
{0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"},
{0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"},
{0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"},
{0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"},
{0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"},
{0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"},
{0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"},
{0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"},
{0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"},
{0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"},
{0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"},
{0x00028230, 0, 0, "PA_SC_EDGERULE"},
{0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"},
{0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"},
{0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"},
{0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"},
};
static const struct radeon_register R600_BLEND_names[] = {
{0x00028414, 0, 0, "CB_BLEND_RED"},
{0x00028418, 0, 0, "CB_BLEND_GREEN"},
{0x0002841C, 0, 0, "CB_BLEND_BLUE"},
{0x00028420, 0, 0, "CB_BLEND_ALPHA"},
{0x00028780, 0, 0, "CB_BLEND0_CONTROL"},
{0x00028784, 0, 0, "CB_BLEND1_CONTROL"},
{0x00028788, 0, 0, "CB_BLEND2_CONTROL"},
{0x0002878C, 0, 0, "CB_BLEND3_CONTROL"},
{0x00028790, 0, 0, "CB_BLEND4_CONTROL"},
{0x00028794, 0, 0, "CB_BLEND5_CONTROL"},
{0x00028798, 0, 0, "CB_BLEND6_CONTROL"},
{0x0002879C, 0, 0, "CB_BLEND7_CONTROL"},
{0x00028804, 0, 0, "CB_BLEND_CONTROL"},
};
static const struct radeon_register R600_DSA_names[] = {
{0x00028028, 0, 0, "DB_STENCIL_CLEAR"},
{0x0002802C, 0, 0, "DB_DEPTH_CLEAR"},
{0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"},
{0x00028430, 0, 0, "DB_STENCILREFMASK"},
{0x00028434, 0, 0, "DB_STENCILREFMASK_BF"},
{0x00028438, 0, 0, "SX_ALPHA_REF"},
{0x000286E0, 0, 0, "SPI_FOG_FUNC_SCALE"},
{0x000286E4, 0, 0, "SPI_FOG_FUNC_BIAS"},
{0x000286DC, 0, 0, "SPI_FOG_CNTL"},
{0x00028800, 0, 0, "DB_DEPTH_CONTROL"},
{0x0002880C, 0, 0, "DB_SHADER_CONTROL"},
{0x00028D0C, 0, 0, "DB_RENDER_CONTROL"},
{0x00028D10, 0, 0, "DB_RENDER_OVERRIDE"},
{0x00028D2C, 0, 0, "DB_SRESULTS_COMPARE_STATE1"},
{0x00028D30, 0, 0, "DB_PRELOAD_CONTROL"},
{0x00028D44, 0, 0, "DB_ALPHA_TO_MASK"},
};
static const struct radeon_register R600_VS_SHADER_names[] = {
{0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"},
{0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"},
{0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"},
{0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"},
{0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"},
{0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"},
{0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"},
{0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"},
{0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"},
{0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"},
{0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"},
{0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"},
{0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"},
{0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"},
{0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"},
{0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"},
{0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"},
{0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"},
{0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"},
{0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"},
{0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"},
{0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"},
{0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"},
{0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"},
{0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"},
{0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"},
{0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"},
{0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"},
{0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"},
{0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"},
{0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"},
{0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"},
{0x00028614, 0, 0, "SPI_VS_OUT_ID_0"},
{0x00028618, 0, 0, "SPI_VS_OUT_ID_1"},
{0x0002861C, 0, 0, "SPI_VS_OUT_ID_2"},
{0x00028620, 0, 0, "SPI_VS_OUT_ID_3"},
{0x00028624, 0, 0, "SPI_VS_OUT_ID_4"},
{0x00028628, 0, 0, "SPI_VS_OUT_ID_5"},
{0x0002862C, 0, 0, "SPI_VS_OUT_ID_6"},
{0x00028630, 0, 0, "SPI_VS_OUT_ID_7"},
{0x00028634, 0, 0, "SPI_VS_OUT_ID_8"},
{0x00028638, 0, 0, "SPI_VS_OUT_ID_9"},
{0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"},
{0x00028858, 1, 0, "SQ_PGM_START_VS"},
{0x00028868, 0, 0, "SQ_PGM_RESOURCES_VS"},
{0x00028894, 1, 1, "SQ_PGM_START_FS"},
{0x000288A4, 0, 0, "SQ_PGM_RESOURCES_FS"},
{0x000288D0, 0, 0, "SQ_PGM_CF_OFFSET_VS"},
{0x000288DC, 0, 0, "SQ_PGM_CF_OFFSET_FS"},
};
static const struct radeon_register R600_PS_SHADER_names[] = {
{0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"},
{0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"},
{0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"},
{0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"},
{0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"},
{0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"},
{0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"},
{0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"},
{0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"},
{0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"},
{0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"},
{0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"},
{0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"},
{0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"},
{0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"},
{0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"},
{0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"},
{0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"},
{0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"},
{0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"},
{0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"},
{0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"},
{0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"},
{0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"},
{0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"},
{0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"},
{0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"},
{0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"},
{0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"},
{0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"},
{0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"},
{0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"},
{0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"},
{0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"},
{0x000286D8, 0, 0, "SPI_INPUT_Z"},
{0x00028840, 1, 0, "SQ_PGM_START_PS"},
{0x00028850, 0, 0, "SQ_PGM_RESOURCES_PS"},
{0x00028854, 0, 0, "SQ_PGM_EXPORTS_PS"},
{0x000288CC, 0, 0, "SQ_PGM_CF_OFFSET_PS"},
};
static const struct radeon_register R600_PS_CONSTANT_names[] = {
{0x00030000, 0, 0, "SQ_ALU_CONSTANT0_0"},
{0x00030004, 0, 0, "SQ_ALU_CONSTANT1_0"},
{0x00030008, 0, 0, "SQ_ALU_CONSTANT2_0"},
{0x0003000C, 0, 0, "SQ_ALU_CONSTANT3_0"},
};
static const struct radeon_register R600_VS_CONSTANT_names[] = {
{0x00031000, 0, 0, "SQ_ALU_CONSTANT0_256"},
{0x00031004, 0, 0, "SQ_ALU_CONSTANT1_256"},
{0x00031008, 0, 0, "SQ_ALU_CONSTANT2_256"},
{0x0003100C, 0, 0, "SQ_ALU_CONSTANT3_256"},
};
static const struct radeon_register R600_UCP_names[] = {
{0x00028e20, 0, 0, "PA_CL_UCP0_X"},
{0x00028e24, 0, 0, "PA_CL_UCP0_Y"},
{0x00028e28, 0, 0, "PA_CL_UCP0_Z"},
{0x00028e2c, 0, 0, "PA_CL_UCP0_W"},
};
static const struct radeon_register R600_PS_RESOURCE_names[] = {
{0x00038000, 0, 0, "RESOURCE0_WORD0"},
{0x00038004, 0, 0, "RESOURCE0_WORD1"},
{0x00038008, 0, 0, "RESOURCE0_WORD2"},
{0x0003800C, 0, 0, "RESOURCE0_WORD3"},
{0x00038010, 0, 0, "RESOURCE0_WORD4"},
{0x00038014, 0, 0, "RESOURCE0_WORD5"},
{0x00038018, 0, 0, "RESOURCE0_WORD6"},
};
static const struct radeon_register R600_VS_RESOURCE_names[] = {
{0x00039180, 0, 0, "RESOURCE160_WORD0"},
{0x00039184, 0, 0, "RESOURCE160_WORD1"},
{0x00039188, 0, 0, "RESOURCE160_WORD2"},
{0x0003918C, 0, 0, "RESOURCE160_WORD3"},
{0x00039190, 0, 0, "RESOURCE160_WORD4"},
{0x00039194, 0, 0, "RESOURCE160_WORD5"},
{0x00039198, 0, 0, "RESOURCE160_WORD6"},
};
static const struct radeon_register R600_FS_RESOURCE_names[] = {
{0x0003A300, 0, 0, "RESOURCE320_WORD0"},
{0x0003A304, 0, 0, "RESOURCE320_WORD1"},
{0x0003A308, 0, 0, "RESOURCE320_WORD2"},
{0x0003A30C, 0, 0, "RESOURCE320_WORD3"},
{0x0003A310, 0, 0, "RESOURCE320_WORD4"},
{0x0003A314, 0, 0, "RESOURCE320_WORD5"},
{0x0003A318, 0, 0, "RESOURCE320_WORD6"},
};
static const struct radeon_register R600_GS_RESOURCE_names[] = {
{0x0003A4C0, 0, 0, "RESOURCE336_WORD0"},
{0x0003A4C4, 0, 0, "RESOURCE336_WORD1"},
{0x0003A4C8, 0, 0, "RESOURCE336_WORD2"},
{0x0003A4CC, 0, 0, "RESOURCE336_WORD3"},
{0x0003A4D0, 0, 0, "RESOURCE336_WORD4"},
{0x0003A4D4, 0, 0, "RESOURCE336_WORD5"},
{0x0003A4D8, 0, 0, "RESOURCE336_WORD6"},
};
static const struct radeon_register R600_PS_SAMPLER_names[] = {
{0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"},
{0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"},
{0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"},
};
static const struct radeon_register R600_VS_SAMPLER_names[] = {
{0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"},
{0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"},
{0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"},
};
static const struct radeon_register R600_GS_SAMPLER_names[] = {
{0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"},
{0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"},
{0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"},
};
static const struct radeon_register R600_PS_SAMPLER_BORDER_names[] = {
{0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
{0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
{0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
{0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
};
static const struct radeon_register R600_VS_SAMPLER_BORDER_names[] = {
{0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
{0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
{0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
{0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
};
static const struct radeon_register R600_GS_SAMPLER_BORDER_names[] = {
{0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
{0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
{0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
{0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
};
static const struct radeon_register R600_CB0_names[] = {
{0x00028040, 1, 0, "CB_COLOR0_BASE"},
{0x000280A0, 0, 0, "CB_COLOR0_INFO"},
{0x00028060, 0, 0, "CB_COLOR0_SIZE"},
{0x00028080, 0, 0, "CB_COLOR0_VIEW"},
{0x000280E0, 1, 1, "CB_COLOR0_FRAG"},
{0x000280C0, 1, 2, "CB_COLOR0_TILE"},
{0x00028100, 0, 0, "CB_COLOR0_MASK"},
};
static const struct radeon_register R600_CB1_names[] = {
{0x00028044, 1, 0, "CB_COLOR1_BASE"},
{0x000280A4, 0, 0, "CB_COLOR1_INFO"},
{0x00028064, 0, 0, "CB_COLOR1_SIZE"},
{0x00028084, 0, 0, "CB_COLOR1_VIEW"},
{0x000280E4, 1, 1, "CB_COLOR1_FRAG"},
{0x000280C4, 1, 2, "CB_COLOR1_TILE"},
{0x00028104, 0, 0, "CB_COLOR1_MASK"},
};
static const struct radeon_register R600_CB2_names[] = {
{0x00028048, 1, 0, "CB_COLOR2_BASE"},
{0x000280A8, 0, 0, "CB_COLOR2_INFO"},
{0x00028068, 0, 0, "CB_COLOR2_SIZE"},
{0x00028088, 0, 0, "CB_COLOR2_VIEW"},
{0x000280E8, 1, 1, "CB_COLOR2_FRAG"},
{0x000280C8, 1, 2, "CB_COLOR2_TILE"},
{0x00028108, 0, 0, "CB_COLOR2_MASK"},
};
static const struct radeon_register R600_CB3_names[] = {
{0x0002804C, 1, 0, "CB_COLOR3_BASE"},
{0x000280AC, 0, 0, "CB_COLOR3_INFO"},
{0x0002806C, 0, 0, "CB_COLOR3_SIZE"},
{0x0002808C, 0, 0, "CB_COLOR3_VIEW"},
{0x000280EC, 1, 1, "CB_COLOR3_FRAG"},
{0x000280CC, 1, 2, "CB_COLOR3_TILE"},
{0x0002810C, 0, 0, "CB_COLOR3_MASK"},
};
static const struct radeon_register R600_CB4_names[] = {
{0x00028050, 1, 0, "CB_COLOR4_BASE"},
{0x000280B0, 0, 0, "CB_COLOR4_INFO"},
{0x00028070, 0, 0, "CB_COLOR4_SIZE"},
{0x00028090, 0, 0, "CB_COLOR4_VIEW"},
{0x000280F0, 1, 1, "CB_COLOR4_FRAG"},
{0x000280D0, 1, 2, "CB_COLOR4_TILE"},
{0x00028110, 0, 0, "CB_COLOR4_MASK"},
};
static const struct radeon_register R600_CB5_names[] = {
{0x00028054, 1, 0, "CB_COLOR5_BASE"},
{0x000280B4, 0, 0, "CB_COLOR5_INFO"},
{0x00028074, 0, 0, "CB_COLOR5_SIZE"},
{0x00028094, 0, 0, "CB_COLOR5_VIEW"},
{0x000280F4, 1, 1, "CB_COLOR5_FRAG"},
{0x000280D4, 1, 2, "CB_COLOR5_TILE"},
{0x00028114, 0, 0, "CB_COLOR5_MASK"},
};
static const struct radeon_register R600_CB6_names[] = {
{0x00028058, 1, 0, "CB_COLOR6_BASE"},
{0x000280B8, 0, 0, "CB_COLOR6_INFO"},
{0x00028078, 0, 0, "CB_COLOR6_SIZE"},
{0x00028098, 0, 0, "CB_COLOR6_VIEW"},
{0x000280F8, 1, 1, "CB_COLOR6_FRAG"},
{0x000280D8, 1, 2, "CB_COLOR6_TILE"},
{0x00028118, 0, 0, "CB_COLOR6_MASK"},
};
static const struct radeon_register R600_CB7_names[] = {
{0x0002805C, 1, 0, "CB_COLOR7_BASE"},
{0x000280BC, 0, 0, "CB_COLOR7_INFO"},
{0x0002807C, 0, 0, "CB_COLOR7_SIZE"},
{0x0002809C, 0, 0, "CB_COLOR7_VIEW"},
{0x000280FC, 1, 1, "CB_COLOR7_FRAG"},
{0x000280DC, 1, 2, "CB_COLOR7_TILE"},
{0x0002811C, 0, 0, "CB_COLOR7_MASK"},
};
static const struct radeon_register R600_DB_names[] = {
{0x0002800C, 1, 0, "DB_DEPTH_BASE"},
{0x00028000, 0, 0, "DB_DEPTH_SIZE"},
{0x00028004, 0, 0, "DB_DEPTH_VIEW"},
{0x00028010, 0, 0, "DB_DEPTH_INFO"},
{0x00028D24, 0, 0, "DB_HTILE_SURFACE"},
{0x00028D34, 0, 0, "DB_PREFETCH_LIMIT"},
};
static const struct radeon_register R600_VGT_names[] = {
{0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"},
{0x00028400, 0, 0, "VGT_MAX_VTX_INDX"},
{0x00028404, 0, 0, "VGT_MIN_VTX_INDX"},
{0x00028408, 0, 0, "VGT_INDX_OFFSET"},
{0x0002840C, 0, 0, "VGT_MULTI_PRIM_IB_RESET_INDX"},
{0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"},
{0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"},
{0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"},
{0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"},
{0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"},
{0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"},
};
static const struct radeon_register R600_DRAW_names[] = {
{0x00008970, 0, 0, "VGT_NUM_INDICES"},
{0x000287E4, 0, 0, "VGT_DMA_BASE_HI"},
{0x000287E8, 1, 0, "VGT_DMA_BASE"},
{0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"},
};
static const struct radeon_register R600_VGT_EVENT_names[] = {
{0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"},
};
static struct radeon_type R600_types[] = {
{ 128, 0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r600_state_pm4_config, R600_CONFIG_names},
{ 128, 1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
{ 128, 2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names},
{ 128, 3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names},
{ 128, 4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names},
{ 128, 5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names},
{ 128, 6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names},
{ 128, 7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names},
{ 128, 8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names},
{ 128, 9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names},
{ 128, 265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names},
{ 128, 521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names},
{ 128, 681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names},
{ 128, 841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names},
{ 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names},
{ 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names},
{ 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names},
{ 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names},
{ 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names},
{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r600_state_pm4_cb0, R600_CB0_names},
{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
{ 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
};
static struct radeon_type R700_types[] = {
{ 128, 0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r700_state_pm4_config, R600_CONFIG_names},
{ 128, 1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
{ 128, 2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names},
{ 128, 3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names},
{ 128, 4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names},
{ 128, 5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names},
{ 128, 6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names},
{ 128, 7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names},
{ 128, 8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names},
{ 128, 9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names},
{ 128, 265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names},
{ 128, 521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names},
{ 128, 681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names},
{ 128, 841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names},
{ 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names},
{ 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names},
{ 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names},
{ 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names},
{ 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names},
{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r700_state_pm4_cb0, R600_CB0_names},
{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
{ 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
};
#endif

44
src/gallium/winsys/r600/drm/radeon.c
View file

@ -153,3 +153,47 @@ struct radeon *radeon_decref(struct radeon *radeon)
free(radeon);
return NULL;
}
int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id)
{
unsigned i, j;
for (i = 0; i < radeon->ntype; i++) {
if (radeon->type[i].range_start) {
if (offset >= radeon->type[i].range_start && offset < radeon->type[i].range_end) {
*typeid = i;
j = offset - radeon->type[i].range_start;
j /= radeon->type[i].stride;
*stateid = radeon->type[i].id + j;
*id = (offset - radeon->type[i].range_start - radeon->type[i].stride * j) / 4;
return 0;
}
} else {
for (j = 0; j < radeon->type[i].nstates; j++) {
if (radeon->type[i].regs[j].offset == offset) {
*typeid = i;
*stateid = radeon->type[i].id;
*id = j;
return 0;
}
}
}
}
fprintf(stderr, "%s unknown register 0x%08X\n", __func__, offset);
return -EINVAL;
}
unsigned radeon_type_from_id(struct radeon *radeon, unsigned id)
{
unsigned i;
for (i = 0; i < radeon->ntype - 1; i++) {
if (radeon->type[i].id == id)
return i;
if (id > radeon->type[i].id && id < radeon->type[i + 1].id)
return i;
}
if (radeon->type[i].id == id)
return i;
return -1;
}

315
src/gallium/winsys/r600/drm/radeon_ctx.c
View file

@ -26,40 +26,54 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include "radeon_priv.h"
#include "radeon_drm.h"
#include "bof.h"
static int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo, unsigned state_id)
int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo)
{
ctx->bo[ctx->nbo].bo = bo;
ctx->bo[ctx->nbo].bo_flushed = 0;
ctx->bo[ctx->nbo].state_id = state_id;
void *ptr;
ptr = realloc(ctx->bo, sizeof(struct radeon_bo) * (ctx->nbo + 1));
if (ptr == NULL) {
return -ENOMEM;
}
ctx->bo = ptr;
ctx->bo[ctx->nbo] = bo;
ctx->nbo++;
return 0;
}
void radeon_ctx_clear(struct radeon_ctx *ctx)
struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc)
{
struct radeon_cs_reloc *greloc;
unsigned i;
/* FIXME somethings is wrong, it should be safe to
* delete bo here, kernel should postpone bo deletion
* until bo is no longer referenced by cs (through the
* fence association)
*/
for (i = 0; i < 50; i++) {
usleep(10);
}
greloc = (void *)(((u8 *)ctx->reloc) + reloc * 4);
for (i = 0; i < ctx->nbo; i++) {
ctx->bo[i].bo = radeon_bo_decref(ctx->radeon, ctx->bo[i].bo);
if (ctx->bo[i]->handle == greloc->handle) {
return radeon_bo_incref(ctx->radeon, ctx->bo[i]);
}
}
fprintf(stderr, "%s no bo for reloc[%d 0x%08X] %d\n", __func__, reloc, greloc->handle, ctx->nbo);
return NULL;
}
void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement)
{
struct radeon_cs_reloc *greloc;
unsigned i;
placement[0] = 0;
placement[1] = 0;
greloc = (void *)(((u8 *)ctx->reloc) + reloc * 4);
for (i = 0; i < ctx->nbo; i++) {
if (ctx->bo[i]->handle == greloc->handle) {
placement[0] = greloc->read_domain | greloc->write_domain;
placement[1] = placement[0];
return;
}
}
ctx->id = 0;
ctx->npm4 = RADEON_CTX_MAX_PM4;
ctx->nreloc = 0;
ctx->nbo = 0;
memset(ctx->state_crc32, 0, ctx->radeon->nstate * 4);
}
struct radeon_ctx *radeon_ctx(struct radeon *radeon)
@ -72,25 +86,6 @@ struct radeon_ctx *radeon_ctx(struct radeon *radeon)
if (ctx == NULL)
return NULL;
ctx->radeon = radeon_incref(radeon);
ctx->max_bo = 4096;
ctx->max_reloc = 4096;
ctx->pm4 = malloc(RADEON_CTX_MAX_PM4 * 4);
if (ctx->pm4 == NULL) {
return radeon_ctx_decref(ctx);
}
ctx->state_crc32 = malloc(ctx->radeon->nstate * 4);
if (ctx->state_crc32 == NULL) {
return radeon_ctx_decref(ctx);
}
ctx->bo = malloc(ctx->max_bo * sizeof(struct radeon_ctx_bo));
if (ctx->bo == NULL) {
return radeon_ctx_decref(ctx);
}
ctx->reloc = malloc(ctx->max_reloc * sizeof(struct radeon_cs_reloc));
if (ctx->reloc == NULL) {
return radeon_ctx_decref(ctx);
}
radeon_ctx_clear(ctx);
return ctx;
}
@ -102,33 +97,31 @@ struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx)
struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx)
{
unsigned i;
if (ctx == NULL)
return NULL;
if (--ctx->refcount > 0) {
return NULL;
}
for (i = 0; i < ctx->ndraw; i++) {
ctx->draw[i] = radeon_draw_decref(ctx->draw[i]);
}
for (i = 0; i < ctx->nbo; i++) {
ctx->bo[i] = radeon_bo_decref(ctx->radeon, ctx->bo[i]);
}
ctx->radeon = radeon_decref(ctx->radeon);
free(ctx->state);
free(ctx->draw);
free(ctx->bo);
free(ctx->pm4);
free(ctx->reloc);
free(ctx->state_crc32);
memset(ctx, 0, sizeof(*ctx));
free(ctx);
return NULL;
}
static int radeon_ctx_bo_id(struct radeon_ctx *ctx, struct radeon_bo *bo)
{
unsigned i;
for (i = 0; i < ctx->nbo; i++) {
if (bo == ctx->bo[i].bo)
return i;
}
return -1;
}
static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *state)
{
unsigned i, j;
@ -138,15 +131,12 @@ static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *stat
return 0;
for (i = 0; i < state->nbo; i++) {
for (j = 0; j < ctx->nbo; j++) {
if (state->bo[i] == ctx->bo[j].bo)
if (state->bo[i] == ctx->bo[j])
break;
}
if (j == ctx->nbo) {
if (ctx->nbo >= ctx->max_bo) {
return -EBUSY;
}
radeon_bo_incref(ctx->radeon, state->bo[i]);
r = radeon_ctx_set_bo_new(ctx, state->bo[i], state->id);
r = radeon_ctx_set_bo_new(ctx, state->bo[i]);
if (r)
return r;
}
@ -154,6 +144,7 @@ static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *stat
return 0;
}
int radeon_ctx_submit(struct radeon_ctx *ctx)
{
struct drm_radeon_cs drmib;
@ -161,17 +152,17 @@ int radeon_ctx_submit(struct radeon_ctx *ctx)
uint64_t chunk_array[2];
int r = 0;
if (!ctx->id)
if (!ctx->cpm4)
return 0;
#if 0
for (r = 0; r < ctx->id; r++) {
for (r = 0; r < ctx->cpm4; r++) {
fprintf(stderr, "0x%08X\n", ctx->pm4[r]);
}
#endif
drmib.num_chunks = 2;
drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
chunks[0].length_dw = ctx->id;
chunks[0].length_dw = ctx->cpm4;
chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
chunks[1].length_dw = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4;
@ -185,10 +176,11 @@ int radeon_ctx_submit(struct radeon_ctx *ctx)
return r;
}
int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
unsigned id, unsigned *placement)
{
unsigned i;
struct radeon_cs_reloc *ptr;
for (i = 0; i < ctx->nreloc; i++) {
if (ctx->reloc[i].handle == bo->handle) {
@ -196,13 +188,14 @@ int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
return 0;
}
}
if (ctx->nreloc >= ctx->max_reloc) {
return -EBUSY;
}
ctx->reloc[ctx->nreloc].handle = bo->handle;
ctx->reloc[ctx->nreloc].read_domain = placement[0] | placement [1];
ctx->reloc[ctx->nreloc].write_domain = placement[0] | placement [1];
ctx->reloc[ctx->nreloc].flags = 0;
ptr = realloc(ctx->reloc, sizeof(struct radeon_cs_reloc) * (ctx->nreloc + 1));
if (ptr == NULL)
return -ENOMEM;
ctx->reloc = ptr;
ptr[ctx->nreloc].handle = bo->handle;
ptr[ctx->nreloc].read_domain = placement[0] | placement [1];
ptr[ctx->nreloc].write_domain = placement[0] | placement [1];
ptr[ctx->nreloc].flags = 0;
ctx->pm4[id] = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4;
ctx->nreloc++;
return 0;
@ -210,90 +203,75 @@ int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state *state)
{
unsigned i, rid, cid;
u32 flags;
int r, bo_id[4];
unsigned i, rid, bid, cid;
int r;
if (state == NULL)
return 0;
for (i = 0; i < state->nbo; i++) {
bo_id[i] = radeon_ctx_bo_id(ctx, state->bo[i]);
if (bo_id[i] < 0) {
return -EINVAL;
}
flags = (~ctx->bo[bo_id[i]].bo_flushed) & ctx->radeon->type[state->id].flush_flags;
if (flags) {
r = ctx->radeon->bo_flush(ctx, state->bo[i], flags, &state->placement[i * 2]);
if (r) {
return r;
}
}
ctx->bo[bo_id[i]].bo_flushed |= ctx->radeon->type[state->id].flush_flags;
}
if ((ctx->radeon->type[state->id].header_cpm4 + state->cpm4) > ctx->npm4) {
/* need to flush */
return -EBUSY;
}
memcpy(&ctx->pm4[ctx->id], ctx->radeon->type[state->id].header_pm4, ctx->radeon->type[state->id].header_cpm4 * 4);
ctx->id += ctx->radeon->type[state->id].header_cpm4;
ctx->npm4 -= ctx->radeon->type[state->id].header_cpm4;
memcpy(&ctx->pm4[ctx->id], state->states, state->cpm4 * 4);
for (i = 0; i < state->nbo; i++) {
memcpy(&ctx->pm4[ctx->id], state->pm4, state->cpm4 * 4);
for (i = 0; i < state->nreloc; i++) {
rid = state->reloc_pm4_id[i];
bid = state->reloc_bo_id[i];
cid = ctx->id + rid;
r = radeon_ctx_reloc(ctx, state->bo[i], cid,
&state->placement[i * 2]);
r = radeon_ctx_reloc(ctx, state->bo[bid], cid,
&state->placement[bid * 2]);
if (r) {
fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->id);
fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->type);
return r;
}
}
ctx->id += state->cpm4;
ctx->npm4 -= state->cpm4;
for (i = 0; i < state->nbo; i++) {
ctx->bo[bo_id[i]].bo_flushed &= ~ctx->radeon->type[state->id].dirty_flags;
}
return 0;
}
int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state)
{
unsigned ndw = 0;
void *tmp;
int r = 0;
/* !!! ONLY ACCEPT QUERY STATE HERE !!! */
if (state->type != R600_QUERY_BEGIN_TYPE && state->type != R600_QUERY_END_TYPE) {
return -EINVAL;
}
r = radeon_state_pm4(state);
if (r)
return r;
/* !!! ONLY ACCEPT QUERY STATE HERE !!! */
ndw = state->cpm4 + ctx->radeon->type[state->id].header_cpm4;
switch (state->id) {
case R600_QUERY_BEGIN:
/* account QUERY_END at same time of QUERY_BEGIN so we know we
* have room left for QUERY_END
*/
if ((ndw * 2) > ctx->npm4) {
/* need to flush */
return -EBUSY;
}
ctx->npm4 -= ndw;
break;
case R600_QUERY_END:
/* add again ndw from previous accounting */
ctx->npm4 += ndw;
break;
default:
if ((ctx->draw_cpm4 + state->cpm4) > RADEON_CTX_MAX_PM4) {
/* need to flush */
return -EBUSY;
}
if (state->cpm4 >= RADEON_CTX_MAX_PM4) {
fprintf(stderr, "%s single state too big %d, max %d\n",
__func__, state->cpm4, RADEON_CTX_MAX_PM4);
return -EINVAL;
}
return radeon_ctx_state_schedule(ctx, state);
tmp = realloc(ctx->state, (ctx->nstate + 1) * sizeof(void*));
if (tmp == NULL)
return -ENOMEM;
ctx->state = tmp;
ctx->state[ctx->nstate++] = radeon_state_incref(state);
/* BEGIN/END query are balanced in the same cs so account for END
* END query when scheduling BEGIN query
*/
if (state->type == R600_QUERY_BEGIN_TYPE) {
ctx->draw_cpm4 += state->cpm4 * 2;
}
return 0;
}
int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw)
{
unsigned i, previous_id;
struct radeon_draw *pdraw = NULL;
struct radeon_draw **ndraw;
struct radeon_state *nstate, *ostate;
unsigned cpm4, i, cstate;
void *tmp;
int r = 0;
ndraw = realloc(ctx->draw, sizeof(void*) * (ctx->ndraw + 1));
if (ndraw == NULL)
return -ENOMEM;
ctx->draw = ndraw;
for (i = 0; i < draw->nstate; i++) {
r = radeon_ctx_state_bo(ctx, draw->state[i]);
if (r)
@ -307,17 +285,76 @@ int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
__func__, draw->cpm4, RADEON_CTX_MAX_PM4);
return -EINVAL;
}
previous_id = ctx->id;
for (i = 0; i < draw->nstate; i++) {
/* FIXME always force draw state to schedule */
if (draw->state[i] && draw->state[i]->pm4_crc != ctx->state_crc32[draw->state[i]->id]) {
r = radeon_ctx_state_schedule(ctx, draw->state[i]);
if (r) {
ctx->id = previous_id;
return r;
tmp = realloc(ctx->state, (ctx->nstate + draw->nstate) * sizeof(void*));
if (tmp == NULL)
return -ENOMEM;
ctx->state = tmp;
pdraw = ctx->cdraw;
for (i = 0, cpm4 = 0, cstate = ctx->nstate; i < draw->nstate - 1; i++) {
nstate = draw->state[i];
if (nstate) {
if (pdraw && pdraw->state[i]) {
ostate = pdraw->state[i];
if (ostate->pm4_crc != nstate->pm4_crc) {
ctx->state[cstate++] = nstate;
cpm4 += nstate->cpm4;
}
} else {
ctx->state[cstate++] = nstate;
cpm4 += nstate->cpm4;
}
}
}
/* The last state is the draw state always add it */
if (draw->state[i] == NULL) {
fprintf(stderr, "%s no draw command\n", __func__);
return -EINVAL;
}
ctx->state[cstate++] = draw->state[i];
cpm4 += draw->state[i]->cpm4;
if ((ctx->draw_cpm4 + cpm4) > RADEON_CTX_MAX_PM4) {
/* need to flush */
return -EBUSY;
}
ctx->draw_cpm4 += cpm4;
ctx->nstate = cstate;
ctx->draw[ctx->ndraw++] = draw;
ctx->cdraw = draw;
return 0;
}
int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
{
int r;
radeon_draw_incref(draw);
r = radeon_ctx_set_draw_new(ctx, draw);
if (r)
radeon_draw_decref(draw);
return r;
}
int radeon_ctx_pm4(struct radeon_ctx *ctx)
{
unsigned i;
int r;
free(ctx->pm4);
ctx->cpm4 = 0;
ctx->pm4 = malloc(ctx->draw_cpm4 * 4);
if (ctx->pm4 == NULL)
return -EINVAL;
for (i = 0, ctx->id = 0; i < ctx->nstate; i++) {
r = radeon_ctx_state_schedule(ctx, ctx->state[i]);
if (r)
return r;
}
if (ctx->id != ctx->draw_cpm4) {
fprintf(stderr, "%s miss predicted pm4 size %d for %d\n",
__func__, ctx->draw_cpm4, ctx->id);
return -EINVAL;
}
ctx->cpm4 = ctx->draw_cpm4;
return 0;
}
@ -347,8 +384,8 @@ printf("%d relocs\n", ctx->nreloc);
bof_decref(blob);
blob = NULL;
/* dump cs */
printf("%d pm4\n", ctx->id);
blob = bof_blob(ctx->id * 4, ctx->pm4);
printf("%d pm4\n", ctx->cpm4);
blob = bof_blob(ctx->cpm4 * 4, ctx->pm4);
if (blob == NULL)
goto out_err;
if (bof_object_set(root, "pm4", blob))
@ -363,23 +400,23 @@ printf("%d pm4\n", ctx->id);
bo = bof_object();
if (bo == NULL)
goto out_err;
size = bof_int32(ctx->bo[i].bo->size);
size = bof_int32(ctx->bo[i]->size);
if (size == NULL)
goto out_err;
if (bof_object_set(bo, "size", size))
goto out_err;
bof_decref(size);
size = NULL;
handle = bof_int32(ctx->bo[i].bo->handle);
handle = bof_int32(ctx->bo[i]->handle);
if (handle == NULL)
goto out_err;
if (bof_object_set(bo, "handle", handle))
goto out_err;
bof_decref(handle);
handle = NULL;
radeon_bo_map(ctx->radeon, ctx->bo[i].bo);
blob = bof_blob(ctx->bo[i].bo->size, ctx->bo[i].bo->data);
radeon_bo_unmap(ctx->radeon, ctx->bo[i].bo);
radeon_bo_map(ctx->radeon, ctx->bo[i]);
blob = bof_blob(ctx->bo[i]->size, ctx->bo[i]->data);
radeon_bo_unmap(ctx->radeon, ctx->bo[i]);
if (blob == NULL)
goto out_err;
if (bof_object_set(bo, "data", blob))

3
src/gallium/winsys/r600/drm/radeon_draw.c
View file

@ -76,6 +76,8 @@ int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state)
{
if (state == NULL)
return 0;
if (state->type >= draw->radeon->ntype)
return -EINVAL;
draw->state[state->id] = radeon_state_decref(draw->state[state->id]);
draw->state[state->id] = state;
return 0;
@ -100,7 +102,6 @@ int radeon_draw_check(struct radeon_draw *draw)
for (i = 0, draw->cpm4 = 0; i < draw->nstate; i++) {
if (draw->state[i]) {
draw->cpm4 += draw->state[i]->cpm4;
draw->cpm4 += draw->radeon->type[draw->state[i]->id].header_cpm4;
}
}
return 0;

36
src/gallium/winsys/r600/drm/radeon_priv.h
View file

@ -30,17 +30,25 @@ struct radeon_ctx;
* radeon functions
*/
typedef int (*radeon_state_pm4_t)(struct radeon_state *state);
struct radeon_type {
const u32 *header_pm4;
const u32 header_cpm4;
const u32 *state_pm4;
const u32 state_cpm4;
const u32 flush_flags;
const u32 dirty_flags;
struct radeon_register {
unsigned offset;
unsigned need_reloc;
unsigned bo_id;
char name[64];
};
typedef int (*radeon_ctx_bo_flush_t)(struct radeon_ctx *ctx, struct radeon_bo *bo, u32 flags, u32 *placement);
struct radeon_type {
unsigned npm4;
unsigned id;
unsigned range_start;
unsigned range_end;
unsigned stride;
unsigned immediate;
char name[64];
unsigned nstates;
radeon_state_pm4_t pm4;
const struct radeon_register *regs;
};
struct radeon {
int fd;
@ -48,8 +56,8 @@ struct radeon {
unsigned device;
unsigned family;
unsigned nstate;
unsigned ntype;
const struct radeon_type *type;
radeon_ctx_bo_flush_t bo_flush;
};
extern struct radeon *radeon_new(int fd, unsigned device);
@ -60,9 +68,12 @@ extern int radeon_is_family_compatible(unsigned family1, unsigned family2);
extern int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id);
extern unsigned radeon_type_from_id(struct radeon *radeon, unsigned id);
int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo);
struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc);
void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement);
int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
int radeon_ctx_draw(struct radeon_ctx *ctx);
int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
unsigned id, unsigned *placement);
/*
* r600/r700 context functions
@ -79,6 +90,7 @@ extern int radeon_state_register_set(struct radeon_state *state, unsigned offset
extern struct radeon_state *radeon_state_duplicate(struct radeon_state *state);
extern int radeon_state_replace_always(struct radeon_state *ostate, struct radeon_state *nstate);
extern int radeon_state_pm4_generic(struct radeon_state *state);
extern int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id);
/*
* radeon draw functions

56
src/gallium/winsys/r600/drm/radeon_state.c
View file

@ -32,29 +32,52 @@
/*
* state core functions
*/
struct radeon_state *radeon_state(struct radeon *radeon, u32 id)
struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
{
struct radeon_state *state;
if (type > radeon->ntype) {
fprintf(stderr, "%s invalid type %d\n", __func__, type);
return NULL;
}
if (id > radeon->nstate) {
fprintf(stderr, "%s invalid state id %d\n", __func__, id);
return NULL;
}
state = calloc(1, sizeof(*state));
if (state == NULL)
return NULL;
state->radeon = radeon;
state->type = type;
state->id = id;
state->refcount = 1;
state->cpm4 = radeon->type[id].state_cpm4;
memcpy(state->states, radeon->type[id].state_pm4, radeon->type[id].state_cpm4 * 4);
state->npm4 = radeon->type[type].npm4;
state->nstates = radeon->type[type].nstates;
state->states = calloc(1, state->nstates * 4);
state->pm4 = calloc(1, radeon->type[type].npm4 * 4);
if (state->states == NULL || state->pm4 == NULL) {
radeon_state_decref(state);
return NULL;
}
return state;
}
struct radeon_state *radeon_state_duplicate(struct radeon_state *state)
{
struct radeon_state *nstate = radeon_state(state->radeon, state->id);
struct radeon_state *nstate = radeon_state(state->radeon, state->type, state->id);
unsigned i;
if (state == NULL)
return NULL;
*nstate = *state;
nstate->cpm4 = state->cpm4;
nstate->nbo = state->nbo;
nstate->nreloc = state->nreloc;
memcpy(nstate->states, state->states, state->nstates * 4);
memcpy(nstate->pm4, state->pm4, state->npm4 * 4);
memcpy(nstate->placement, state->placement, 8 * 4);
memcpy(nstate->reloc_pm4_id, state->reloc_pm4_id, 8 * 4);
memcpy(nstate->reloc_bo_id, state->reloc_bo_id, 8 * 4);
memcpy(nstate->bo_dirty, state->bo_dirty, 4 * 4);
for (i = 0; i < state->nbo; i++) {
nstate->bo[i] = radeon_bo_incref(state->radeon, state->bo[i]);
}
@ -79,6 +102,9 @@ struct radeon_state *radeon_state_decref(struct radeon_state *state)
for (i = 0; i < state->nbo; i++) {
state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]);
}
free(state->immd);
free(state->states);
free(state->pm4);
memset(state, 0, sizeof(*state));
free(state);
return NULL;
@ -119,8 +145,24 @@ static u32 crc32(void *d, size_t len)
int radeon_state_pm4(struct radeon_state *state)
{
if (state == NULL)
int r;
if (state == NULL || state->cpm4)
return 0;
state->pm4_crc = crc32(state->states, state->cpm4 * 4);
r = state->radeon->type[state->type].pm4(state);
if (r) {
fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n",
__func__, state->type, state->id);
return r;
}
state->pm4_crc = crc32(state->pm4, state->cpm4 * 4);
return 0;
}
int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id)
{
state->reloc_pm4_id[state->nreloc] = id;
state->reloc_bo_id[state->nreloc] = bo_id;
state->nreloc++;
return 0;
}