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anv: Flush untyped dataport cache when HDC flush is requested on compute

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In the Intel(R) Arc(tm) A-Series Graphics and Intel Data Center GPU
Flex Series Open-Source Programmer's Reference Manual, Vol 2a: Command
Reference: Instructions, PIPE_CONTROL, HDC Pipeline Flush (DWord 0,
Bit 9), there is a programming note:

> When the "Pipeline Select" mode is set to "GPGPU", the LSC Untyped
> L1 cache flush is controlled by "Untyped Data-Port Cache Flush" bit
> in the PIPE_CONTROL command.

Ref: a8108f1d44 ("anv: Add missing untyped data port flush on PIPELINE_SELECT")
Ref: bd8e8d204d ("iris: Add missing untyped data port flush on PIPELINE_SELECT")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23176>
This commit is contained in:
Jordan Justen 2023-05-15 14:53:03 -04:00 • committed by Marge Bot
parent c5ca2bed51
commit 215c6c6ce4
1 changed files with 3 additions and 0 deletions
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3
src/intel/vulkan/genX_cmd_buffer.c
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@ -1560,6 +1560,9 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
*/
if (current_pipeline != GPGPU) {
flush_bits &= ~ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
} else {
if (flush_bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT)
flush_bits |= ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
}
if (flush_bits & ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT)