fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-03-11 17:50:32 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

ac/gpu_info: compute the best safe IB alignment

Browse source 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
This commit is contained in:
Marek Olšák 2020-05-17 02:38:02 -04:00
parent 5f365affc9
commit 21504eab78
4 changed files with 17 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
src/amd/common/ac_gpu_info.c
View file

@ -648,16 +648,28 @@ bool ac_query_gpu_info(int fd, void *dev_p,
unsigned ib_align = 0;
ib_align = MAX2(ib_align, gfx.ib_start_alignment);
ib_align = MAX2(ib_align, gfx.ib_size_alignment);
ib_align = MAX2(ib_align, compute.ib_start_alignment);
ib_align = MAX2(ib_align, compute.ib_size_alignment);
ib_align = MAX2(ib_align, dma.ib_start_alignment);
ib_align = MAX2(ib_align, dma.ib_size_alignment);
ib_align = MAX2(ib_align, uvd.ib_start_alignment);
ib_align = MAX2(ib_align, uvd.ib_size_alignment);
ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
ib_align = MAX2(ib_align, uvd_enc.ib_size_alignment);
ib_align = MAX2(ib_align, vce.ib_start_alignment);
ib_align = MAX2(ib_align, vce.ib_size_alignment);
ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_dec.ib_size_alignment);
ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_enc.ib_size_alignment);
ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_jpeg.ib_size_alignment);
/* GFX10 and maybe GFX9 need this alignment for cache coherency. */
if (info->chip_class >= GFX9)
ib_align = MAX2(ib_align, info->tcc_cache_line_size);
assert(ib_align);
info->ib_start_alignment = ib_align;
info->ib_alignment = ib_align;
if ((info->drm_minor >= 31 &&
(info->family == CHIP_RAVEN ||
@ -855,7 +867,7 @@ void ac_print_gpu_info(struct radeon_info *info)
printf("CP info:\n");
printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
printf(" ib_start_alignment = %u\n", info->ib_start_alignment);
printf(" ib_alignment = %u\n", info->ib_alignment);
printf(" me_fw_version = %i\n", info->me_fw_version);
printf(" me_fw_feature = %i\n", info->me_fw_feature);
printf(" pfp_fw_version = %i\n", info->pfp_fw_version);

2
src/amd/common/ac_gpu_info.h
View file

@ -110,7 +110,7 @@ struct radeon_info {
/* CP info. */
bool gfx_ib_pad_with_type2;
unsigned ib_start_alignment;
unsigned ib_alignment; /* both start and size alignment */
uint32_t me_fw_version;
uint32_t me_fw_feature;
uint32_t pfp_fw_version;

2
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
View file

@ -831,7 +831,7 @@ static void amdgpu_ib_finalize(struct amdgpu_winsys *ws, struct amdgpu_ib *ib)
{
amdgpu_set_ib_size(ib);
ib->used_ib_space += ib->base.current.cdw * 4;
ib->used_ib_space = align(ib->used_ib_space, ws->info.ib_start_alignment);
ib->used_ib_space = align(ib->used_ib_space, ws->info.ib_alignment);
ib->max_ib_size = MAX2(ib->max_ib_size, ib->base.prev_dw + ib->base.current.cdw);
}

2
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View file

@ -569,7 +569,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
(ws->info.family == CHIP_HAWAII &&
ws->accel_working2 < 3);
ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
ws->info.ib_start_alignment = 4096;
ws->info.ib_alignment = 4096;
ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
/* HTILE is broken with 1D tiling on old kernels and GFX7. */
ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != GFX7 ||