fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-06-21 08:08:24 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

nir/opt_shrink_stores: Don't shrink ivec2 stores to int64 images

Browse source 
This prevents regressions in r64 image store tests when the Intel
compilers enable the use of nir_opt_shrink_stores. On all platforms, ANV
lower stores in r64 image stores to write an ivec2 instead of an int64.

As an alternative, I did consider adding a callback. This would have
been very invasive, and it seemed really heavy handed.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41940>
This commit is contained in:
Ian Romanick 2026-06-10 08:44:58 -07:00 • committed by Marge Bot
parent 41b4e04c76
commit 213ca7d8e8
1 changed files with 11 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
src/compiler/nir/nir_opt_shrink_stores.c
View file

@ -48,6 +48,17 @@ opt_shrink_vectors_image_store(nir_builder *b, nir_intrinsic_instr *instr)
if (components >= instr->num_components)
return false;
if (components == 1) {
/* Some platforms split int64 writes into an ivec2 writes. Since the
* number of bits is the expected amount, don't trim any components.
*/
const unsigned bits_written = instr->num_components *
instr->src[3].ssa->bit_size;
if (util_format_get_blocksizebits(format) == bits_written)
return false;
}
nir_def *data = nir_trim_vector(b, instr->src[3].ssa, components);
nir_src_rewrite(&instr->src[3], data);
instr->num_components = components;