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nir_to_tgsi: Fix assertion failures handling 64-bit vec3/vec4 ssa undefs.

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Found in virgl, where a glslparsertest accidentally gets its inputs
lowered to undefs, and 64-bit undefs don't get split by the normal
alu/intrinsic splitter (and would be hard to split because other passes
would see reconstruction of the vec4 from undefs and turn it back into
vec3/vec4 undef).

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16043>
This commit is contained in:
Emma Anholt 2022-03-30 15:57:34 -07:00 • committed by Marge Bot
parent 4850dbb3f9
commit 21282879f9
1 changed files with 6 additions and 1 deletions
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7
src/gallium/auxiliary/nir/nir_to_tgsi.c
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@ -1160,7 +1160,12 @@ ntt_get_alu_src(struct ntt_compile *c, nir_alu_instr *instr, int i)
nir_alu_src src = instr->src[i];
struct ureg_src usrc = ntt_get_src(c, src.src);
if (nir_src_bit_size(src.src) == 64) {
/* Expand double/dvec2 src references to TGSI swizzles using a pair of 32-bit
* channels. We skip this for undefs, as those don't get split to vec2s (but
* the specific swizzles from an undef don't matter)
*/
if (nir_src_bit_size(src.src) == 64 &&
!(src.src.is_ssa && src.src.ssa->parent_instr->type == nir_instr_type_ssa_undef)) {
int chan0 = 0, chan1 = 1;
if (nir_op_infos[instr->op].input_sizes[i] == 0) {
chan0 = ffs(instr->dest.write_mask) - 1;