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intel/blorp: Convert blorp_clear color_write_disable to a bitmask

Browse source 
Reworks:
 * Various cleanups adding BITFIELD_* (s-b Jason)
 * Add /* color_write_disable */ comment (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
This commit is contained in:
Jordan Justen 2021-09-16 14:25:42 -07:00 • committed by Marge Bot
parent 00ea664cb6
commit 2123d59693
8 changed files with 30 additions and 45 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/gallium/drivers/crocus/crocus_clear.c
View file

@ -360,7 +360,6 @@ clear_color(struct crocus_context *ice,
return;
}
bool color_write_disable[4] = { false, false, false, false };
enum isl_aux_usage aux_usage =
crocus_resource_render_aux_usage(ice, res, level, format, false);
@ -381,7 +380,7 @@ clear_color(struct crocus_context *ice,
blorp_clear(&blorp_batch, &surf, format, swizzle,
level, box->z, box->depth, box->x, box->y,
box->x + box->width, box->y + box->height,
color, color_write_disable);
color, 0 /* color_write_disable */);
blorp_batch_finish(&blorp_batch);
crocus_flush_and_dirty_for_history(ice, batch, res,

3
src/gallium/drivers/iris/iris_clear.c
View file

@ -375,7 +375,6 @@ clear_color(struct iris_context *ice,
return;
}
bool color_write_disable[4] = { false, false, false, false };
enum isl_aux_usage aux_usage =
iris_resource_render_aux_usage(ice, res, level, format, false);
@ -399,7 +398,7 @@ clear_color(struct iris_context *ice,
blorp_clear(&blorp_batch, &surf, format, swizzle,
level, box->z, box->depth, box->x, box->y,
box->x + box->width, box->y + box->height,
color, color_write_disable);
color, 0 /* color_write_disable */);
blorp_batch_finish(&blorp_batch);
iris_batch_sync_region_end(batch);

2
src/intel/blorp/blorp.h
View file

@ -180,7 +180,7 @@ blorp_clear(struct blorp_batch *batch,
uint32_t level, uint32_t start_layer, uint32_t num_layers,
uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1,
union isl_color_value clear_color,
const bool color_write_disable[4]);
uint8_t color_write_disable);
void
blorp_clear_depth_stencil(struct blorp_batch *batch,

12
src/intel/blorp/blorp_clear.c
View file

@ -377,7 +377,7 @@ blorp_clear(struct blorp_batch *batch,
uint32_t level, uint32_t start_layer, uint32_t num_layers,
uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1,
union isl_color_value clear_color,
const bool color_write_disable[4])
uint8_t color_write_disable)
{
struct blorp_params params;
blorp_params_init(&params);
@ -434,13 +434,9 @@ blorp_clear(struct blorp_batch *batch,
/* Constant color writes ignore everyting in blend and color calculator
* state. This is not documented.
*/
if (color_write_disable) {
for (unsigned i = 0; i < 4; i++) {
params.color_write_disable[i] = color_write_disable[i];
if (color_write_disable[i])
use_simd16_replicated_data = false;
}
}
params.color_write_disable = color_write_disable & BITFIELD_MASK(4);
if (color_write_disable)
use_simd16_replicated_data = false;
if (!blorp_params_get_clear_kernel(batch, &params,
use_simd16_replicated_data,

20
src/intel/blorp/blorp_genX_exec.h
View file

@ -1111,10 +1111,10 @@ blorp_emit_blend_state(struct blorp_batch *batch,
.PostBlendColorClampEnable = true,
.ColorClampRange = COLORCLAMP_RTFORMAT,
.WriteDisableRed = params->color_write_disable[0],
.WriteDisableGreen = params->color_write_disable[1],
.WriteDisableBlue = params->color_write_disable[2],
.WriteDisableAlpha = params->color_write_disable[3],
.WriteDisableRed = params->color_write_disable & 1,
.WriteDisableGreen = params->color_write_disable & 2,
.WriteDisableBlue = params->color_write_disable & 4,
.WriteDisableAlpha = params->color_write_disable & 8,
};
GENX(BLEND_STATE_ENTRY_pack)(NULL, pos, &entry);
pos += GENX(BLEND_STATE_ENTRY_length);
@ -1424,7 +1424,7 @@ blorp_emit_surface_state(struct blorp_batch *batch,
const struct brw_blorp_surface_info *surface,
UNUSED enum isl_aux_op aux_op,
void *state, uint32_t state_offset,
const bool color_write_disables[4],
uint8_t color_write_disable,
bool is_render_target)
{
const struct isl_device *isl_dev = batch->blorp->isl_dev;
@ -1451,13 +1451,13 @@ blorp_emit_surface_state(struct blorp_batch *batch,
isl_channel_mask_t write_disable_mask = 0;
if (is_render_target && GFX_VER <= 5) {
if (color_write_disables[0])
if (color_write_disable & BITFIELD_BIT(0))
write_disable_mask |= ISL_CHANNEL_RED_BIT;
if (color_write_disables[1])
if (color_write_disable & BITFIELD_BIT(1))
write_disable_mask |= ISL_CHANNEL_GREEN_BIT;
if (color_write_disables[2])
if (color_write_disable & BITFIELD_BIT(2))
write_disable_mask |= ISL_CHANNEL_BLUE_BIT;
if (color_write_disables[3])
if (color_write_disable & BITFIELD_BIT(3))
write_disable_mask |= ISL_CHANNEL_ALPHA_BIT;
}
@ -1592,7 +1592,7 @@ blorp_setup_binding_table(struct blorp_batch *batch,
params->fast_clear_op,
surface_maps[BLORP_TEXTURE_BT_INDEX],
surface_offsets[BLORP_TEXTURE_BT_INDEX],
NULL, false);
0, false);
if (params->src.clear_color_addr.buffer != NULL)
has_indirect_clear_color = true;
}

2
src/intel/blorp/blorp_priv.h
View file

@ -219,7 +219,7 @@ struct blorp_params
enum isl_aux_op hiz_op;
bool full_surface_hiz_op;
enum isl_aux_op fast_clear_op;
bool color_write_disable[4];
uint8_t color_write_disable;
struct brw_blorp_wm_inputs wm_inputs;
struct blorp_vs_inputs vs_inputs;
bool dst_clear_color_as_input;

16
src/intel/vulkan/anv_blorp.c
View file

@ -965,7 +965,7 @@ void anv_CmdFillBuffer(
blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
0, 0, 1, 0, 0, MAX_SURFACE_DIM, MAX_SURFACE_DIM,
color, NULL);
color, 0 /* color_write_disable */);
fillSize -= max_fill_size;
dstOffset += max_fill_size;
}
@ -982,7 +982,7 @@ void anv_CmdFillBuffer(
blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
0, 0, 1, 0, 0, MAX_SURFACE_DIM, height,
color, NULL);
color, 0 /* color_write_disable */);
fillSize -= rect_fill_size;
dstOffset += rect_fill_size;
}
@ -997,7 +997,7 @@ void anv_CmdFillBuffer(
blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
0, 0, 1, 0, 0, width, 1,
color, NULL);
color, 0 /* color_write_disable */);
}
blorp_batch_finish(&batch);
@ -1016,8 +1016,6 @@ void anv_CmdClearColorImage(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_image, image, _image);
static const bool color_write_disable[4] = { false, false, false, false };
struct blorp_batch batch;
blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
@ -1063,7 +1061,7 @@ void anv_CmdClearColorImage(
src_format.isl_format, src_format.swizzle,
level, base_layer, layer_count,
0, 0, level_width, level_height,
vk_to_isl_color(*pColor), color_write_disable);
vk_to_isl_color(*pColor), 0 /* color_write_disable */);
}
}
@ -1145,7 +1143,7 @@ void anv_CmdClearDepthStencilImage(
ISL_FORMAT_R8_UINT, ISL_SWIZZLE_IDENTITY,
level, base_layer, layer_count,
0, 0, level_width, level_height,
stencil_color, NULL);
stencil_color, 0 /* color_write_disable */);
}
}
}
@ -1595,7 +1593,7 @@ anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
area.offset.x, area.offset.y,
area.offset.x + area.extent.width,
area.offset.y + area.extent.height,
clear_color, NULL);
clear_color, 0 /* color_write_disable */);
blorp_batch_finish(&batch);
}
@ -1677,7 +1675,7 @@ anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
area.offset.x, area.offset.y,
area.offset.x + area.extent.width,
area.offset.y + area.extent.height,
stencil_color, NULL);
stencil_color, 0 /* color_write_disable */);
}
blorp_batch_finish(&batch);

17
src/mesa/drivers/dri/i965/brw_blorp.c
View file

@ -1165,7 +1165,7 @@ err:
static bool
set_write_disables(const struct brw_renderbuffer *irb,
const unsigned color_mask, bool *color_write_disable)
const unsigned color_mask, uint8_t *color_write_disable)
{
/* Format information in the renderbuffer represents the requirements
* given by the client. There are cases where the backing miptree uses,
@ -1174,16 +1174,9 @@ set_write_disables(const struct brw_renderbuffer *irb,
*/
const GLenum base_format = irb->Base.Base._BaseFormat;
const int components = _mesa_components_in_format(base_format);
bool disables = false;
assert(components > 0);
for (int i = 0; i < components; i++) {
color_write_disable[i] = !(color_mask & (1 << i));
disables = disables || color_write_disable[i];
}
return disables;
*color_write_disable = ~color_mask & BITFIELD_MASK(components);
return *color_write_disable;
}
static void
@ -1219,9 +1212,9 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
if (INTEL_DEBUG & DEBUG_NO_FAST_CLEAR)
can_fast_clear = false;
bool color_write_disable[4] = { false, false, false, false };
uint8_t color_write_disable = 0;
if (set_write_disables(irb, GET_COLORMASK(ctx->Color.ColorMask, buf),
color_write_disable))
&color_write_disable))
can_fast_clear = false;
/* We store clear colors as floats or uints as needed. If there are