radeonsi: clamp cp prefetch size

Limit the size instead of asserting that the size (which comes
from the shader bo) is smaller.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15184
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41264>
This commit is contained in:
Pierre-Eric Pelloux-Prayer 2026-03-31 16:07:31 +02:00
parent c1f1b704d9
commit 20b0349b05

View file

@ -636,8 +636,7 @@ static void si_cp_dma_prefetch_inline(struct radeon_cmdbuf *cs, uint64_t address
{
assert(GFX_VERSION >= GFX7);
if (GFX_VERSION >= GFX11)
size = MIN2(size, 32768 - SI_CPDMA_ALIGNMENT);
size = MIN2(size, 32768 - SI_CPDMA_ALIGNMENT);
/* The prefetch address and size must be aligned, so that we don't have to apply
* the complicated hw bug workaround.
@ -647,7 +646,6 @@ static void si_cp_dma_prefetch_inline(struct radeon_cmdbuf *cs, uint64_t address
*/
assert(size % SI_CPDMA_ALIGNMENT == 0);
assert(address % SI_CPDMA_ALIGNMENT == 0);
assert(size < S_415_BYTE_COUNT(~0u));
assert(address || size == 0);
uint32_t header = S_501_SRC_SEL(V_501_SRC_ADDR_USING_L2);