From 20445f296bfcf3be40436617aad5d8378ad09bce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 26 Feb 2024 21:08:51 -0500 Subject: [PATCH] radeonsi: disable binning correctly on gfx11.5 Fixes: b44a886b84c - amd/common: add registers for gfx11.5 Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_state_binning.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c index 39a97ebd0ce..984586eb864 100644 --- a/src/gallium/drivers/radeonsi/si_state_binning.c +++ b/src/gallium/drivers/radeonsi/si_state_binning.c @@ -393,6 +393,9 @@ static void si_emit_dpbb_disable(struct si_context *sctx) if (sctx->gfx_level >= GFX10) { struct uvec2 bin_size = {}; struct uvec2 bin_size_extend = {}; + unsigned binning_disabled = + sctx->gfx_level >= GFX11_5 ? V_028C44_BINNING_DISABLED + : V_028C44_DISABLE_BINNING_USE_NEW_SC; bin_size.x = 128; bin_size.y = sctx->framebuffer.min_bytes_per_pixel <= 4 ? 128 : 64; @@ -404,7 +407,7 @@ static void si_emit_dpbb_disable(struct si_context *sctx) radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0, - S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) | + S_028C44_BINNING_MODE(binning_disabled) | S_028C44_BIN_SIZE_X(bin_size.x == 16) | S_028C44_BIN_SIZE_Y(bin_size.y == 16) | S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |