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amd,radv,radeonsi: add ac_emit_cp_spi_config_cntl()

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37956>
This commit is contained in:
Samuel Pitoiset 2025-10-20 12:49:52 +02:00 • committed by Marge Bot
parent 5cb400a97b
commit 202f8db793
6 changed files with 37 additions and 55 deletions
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28
src/amd/common/ac_cmdbuf_cp.c
View file

@ -501,3 +501,31 @@ ac_emit_cp_inhibit_clockgating(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_leve
} }
ac_cmdbuf_end(); ac_cmdbuf_end();
} }
void
ac_emit_cp_spi_config_cntl(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level,
bool enable)
{
ac_cmdbuf_begin(cs);
if (gfx_level >= GFX12) {
ac_cmdbuf_set_uconfig_reg(R_031120_SPI_SQG_EVENT_CTL,
S_031120_ENABLE_SQG_TOP_EVENTS(enable) |
S_031120_ENABLE_SQG_BOP_EVENTS(enable));
} else if (gfx_level >= GFX9) {
uint32_t spi_config_cntl = S_031100_GPR_WRITE_PRIORITY(0x2c688) |
S_031100_EXP_PRIORITY_ORDER(3) |
S_031100_ENABLE_SQG_TOP_EVENTS(enable) |
S_031100_ENABLE_SQG_BOP_EVENTS(enable);
if (gfx_level >= GFX10)
spi_config_cntl |= S_031100_PS_PKR_PRIORITY_CNTL(3);
ac_cmdbuf_set_uconfig_reg(R_031100_SPI_CONFIG_CNTL, spi_config_cntl);
} else {
/* SPI_CONFIG_CNTL is a protected register on GFX6-GFX8. */
ac_cmdbuf_set_privileged_config_reg(R_009100_SPI_CONFIG_CNTL,
S_009100_ENABLE_SQG_TOP_EVENTS(enable) |
S_009100_ENABLE_SQG_BOP_EVENTS(enable));
}
ac_cmdbuf_end();
}

4
src/amd/common/ac_cmdbuf_cp.h
View file

@ -116,6 +116,10 @@ void
ac_emit_cp_inhibit_clockgating(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level, ac_emit_cp_inhibit_clockgating(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level,
bool inhibit); bool inhibit);
void
ac_emit_cp_spi_config_cntl(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level,
bool enable);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

4
src/amd/vulkan/radv_perfcounter.c
View file

@ -685,7 +685,7 @@ radv_pc_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_pc_query_poo
radv_pc_wait_idle(cmd_buffer); radv_pc_wait_idle(cmd_buffer);
radv_perfcounter_emit_reset(cs, false); radv_perfcounter_emit_reset(cs, false);
ac_emit_cp_inhibit_clockgating(cs->b, pdev->info.gfx_level, true); ac_emit_cp_inhibit_clockgating(cs->b, pdev->info.gfx_level, true);
radv_emit_spi_config_cntl(device, cs, true); ac_emit_cp_spi_config_cntl(cs->b, pdev->info.gfx_level, true);
radv_perfcounter_emit_shaders(device, cs, 0x7f); radv_perfcounter_emit_shaders(device, cs, 0x7f);
for (unsigned pass = 0; pass < pool->num_passes; ++pass) { for (unsigned pass = 0; pass < pool->num_passes; ++pass) {
@ -751,7 +751,7 @@ radv_pc_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_pc_query_pool
radv_pc_wait_idle(cmd_buffer); radv_pc_wait_idle(cmd_buffer);
radv_pc_stop_and_sample(cmd_buffer, pool, va, true); radv_pc_stop_and_sample(cmd_buffer, pool, va, true);
radv_perfcounter_emit_reset(cs, false); radv_perfcounter_emit_reset(cs, false);
radv_emit_spi_config_cntl(device, cs, false); ac_emit_cp_spi_config_cntl(cs->b, pdev->info.gfx_level, false);
ac_emit_cp_inhibit_clockgating(cs->b, pdev->info.gfx_level, false); ac_emit_cp_inhibit_clockgating(cs->b, pdev->info.gfx_level, false);
assert(cs->b->cdw <= cdw_max); assert(cs->b->cdw <= cdw_max);

31
src/amd/vulkan/radv_sqtt.c
View file

@ -132,33 +132,6 @@ radv_emit_sqtt_userdata(const struct radv_cmd_buffer *cmd_buffer, const void *da
} }
} }
void
radv_emit_spi_config_cntl(const struct radv_device *device, struct radv_cmd_stream *cs, bool enable)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
radeon_begin(cs);
if (pdev->info.gfx_level >= GFX12) {
radeon_set_uconfig_reg(R_031120_SPI_SQG_EVENT_CTL,
S_031120_ENABLE_SQG_TOP_EVENTS(enable) | S_031120_ENABLE_SQG_BOP_EVENTS(enable));
} else if (pdev->info.gfx_level >= GFX9) {
uint32_t spi_config_cntl = S_031100_GPR_WRITE_PRIORITY(0x2c688) | S_031100_EXP_PRIORITY_ORDER(3) |
S_031100_ENABLE_SQG_TOP_EVENTS(enable) | S_031100_ENABLE_SQG_BOP_EVENTS(enable);
if (pdev->info.gfx_level >= GFX10)
spi_config_cntl |= S_031100_PS_PKR_PRIORITY_CNTL(3);
radeon_set_uconfig_reg(R_031100_SPI_CONFIG_CNTL, spi_config_cntl);
} else {
/* SPI_CONFIG_CNTL is a protected register on GFX6-GFX8. */
radeon_set_privileged_config_reg(R_009100_SPI_CONFIG_CNTL,
S_009100_ENABLE_SQG_TOP_EVENTS(enable) | S_009100_ENABLE_SQG_BOP_EVENTS(enable));
}
radeon_end();
}
VkResult VkResult
radv_sqtt_acquire_gpu_timestamp(struct radv_device *device, struct radeon_winsys_bo **gpu_timestamp_bo, radv_sqtt_acquire_gpu_timestamp(struct radv_device *device, struct radeon_winsys_bo **gpu_timestamp_bo,
uint32_t *gpu_timestamp_offset, void **gpu_timestamp_ptr) uint32_t *gpu_timestamp_offset, void **gpu_timestamp_ptr)
@ -523,7 +496,7 @@ radv_begin_sqtt(struct radv_queue *queue)
ac_emit_cp_inhibit_clockgating(cs.b, pdev->info.gfx_level, true); ac_emit_cp_inhibit_clockgating(cs.b, pdev->info.gfx_level, true);
/* Enable SQG events that collects thread trace data. */ /* Enable SQG events that collects thread trace data. */
radv_emit_spi_config_cntl(device, &cs, true); ac_emit_cp_spi_config_cntl(cs.b, pdev->info.gfx_level, true);
radv_perfcounter_emit_reset(&cs, true); radv_perfcounter_emit_reset(&cs, true);
@ -610,7 +583,7 @@ radv_end_sqtt(struct radv_queue *queue)
radv_perfcounter_emit_reset(&cs, true); radv_perfcounter_emit_reset(&cs, true);
/* Restore previous state by disabling SQG events. */ /* Restore previous state by disabling SQG events. */
radv_emit_spi_config_cntl(device, &cs, false); ac_emit_cp_spi_config_cntl(cs.b, pdev->info.gfx_level, false);
/* Restore previous state by re-enabling clock gating. */ /* Restore previous state by re-enabling clock gating. */
ac_emit_cp_inhibit_clockgating(cs.b, pdev->info.gfx_level, false); ac_emit_cp_inhibit_clockgating(cs.b, pdev->info.gfx_level, false);

2
src/amd/vulkan/radv_sqtt.h
View file

@ -65,8 +65,6 @@ bool radv_sqtt_queue_events_enabled(void);
void radv_emit_sqtt_userdata(const struct radv_cmd_buffer *cmd_buffer, const void *data, uint32_t num_dwords); void radv_emit_sqtt_userdata(const struct radv_cmd_buffer *cmd_buffer, const void *data, uint32_t num_dwords);
void radv_emit_spi_config_cntl(const struct radv_device *device, struct radv_cmd_stream *cs, bool enable);
VkResult radv_sqtt_acquire_gpu_timestamp(struct radv_device *device, struct radeon_winsys_bo **gpu_timestamp_bo, VkResult radv_sqtt_acquire_gpu_timestamp(struct radv_device *device, struct radeon_winsys_bo **gpu_timestamp_bo,
uint32_t *gpu_timestamp_offset, void **gpu_timestamp_ptr); uint32_t *gpu_timestamp_offset, void **gpu_timestamp_ptr);

23
src/gallium/drivers/radeonsi/si_sqtt.c
View file

@ -529,28 +529,7 @@ static void
si_emit_spi_config_cntl(struct si_context *sctx, si_emit_spi_config_cntl(struct si_context *sctx,
struct radeon_cmdbuf *cs, bool enable) struct radeon_cmdbuf *cs, bool enable)
{ {
radeon_begin(cs); ac_emit_cp_spi_config_cntl(&cs->current, sctx->gfx_level, enable);
if (sctx->gfx_level >= GFX12) {
radeon_set_uconfig_reg(R_031120_SPI_SQG_EVENT_CTL,
S_031120_ENABLE_SQG_TOP_EVENTS(enable) | S_031120_ENABLE_SQG_BOP_EVENTS(enable));
} else if (sctx->gfx_level >= GFX9) {
uint32_t spi_config_cntl = S_031100_GPR_WRITE_PRIORITY(0x2c688) |
S_031100_EXP_PRIORITY_ORDER(3) |
S_031100_ENABLE_SQG_TOP_EVENTS(enable) |
S_031100_ENABLE_SQG_BOP_EVENTS(enable);
if (sctx->gfx_level >= GFX10)
spi_config_cntl |= S_031100_PS_PKR_PRIORITY_CNTL(3);
radeon_set_uconfig_reg(R_031100_SPI_CONFIG_CNTL, spi_config_cntl);
} else {
/* SPI_CONFIG_CNTL is a protected register on GFX6-GFX8. */
radeon_set_privileged_config_reg(R_009100_SPI_CONFIG_CNTL,
S_009100_ENABLE_SQG_TOP_EVENTS(enable) |
S_009100_ENABLE_SQG_BOP_EVENTS(enable));
}
radeon_end();
} }
static uint32_t num_events = 0; static uint32_t num_events = 0;